Add delay in assertion from array

SystemVerilog
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1

Hi,

I have a scenario in which i have to add delay in an assertion from an array.
The problem statement is when ip =1 then after the specific delay from array op=1.

Delay value can be 0 as well. In that case ip=op on the same clock.

$rose(ip) |-> !op ##dealy_ar[0] $rose(op)

2

In reply to qwerty:

##delay_ar[0] will wait for that specific number of clock ticks.

$rose(ip) |-> ##dealy_ar[0] $rose(op) will check that posedge of op should be after delay_ar[0] clock ticks from posedge of ip. If delay_ar[0] is 0 then both ip and op should be asserted as same clock tick.

3

In reply to Dharmendram:

But we cannot use the array for delay. Also we have to make sure that the op is unchanged till delay.