I am trying to verify a sMEM design using assertions in systemVerilog however I got a problem I did not Know How to solve it :
I am supposed to verify if:
On rising edge of CLKA, when BLKA is 1 and RWA is 1, d_ata is read at ADDRA address of the RAM_ and the result is available at DOUTA.
in my design the RAM is defined as shared variable
so how can I write the assertions ?