Access register name incremental in a loop

SystemVerilog
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1

Hi,

I have 4 registers names like reg0,reg1,reg2,reg3.
How can i access them in for loop?
like
for(i=0;i<4;i++)
data = reg;

2

In reply to jyotsna:

Use generate statement

3

In reply to haykp:

In reply to jyotsna:
Use generate statement

Please provide example.

4

In reply to jyotsna:

SystemVerilog does not allow you to compose identifier names dynamically, you must use an array.