Is ##2 legal within a sequence or property expression?

Hi ,
Generally I observe ##1 used between sequences within a property or sequence expression .
I was curious whether ##N is legal ? ( where N is elaboration-time constant and N > 1 )


module  top;

  bit  clk0  ;

  always  #5  clk0  =  ! clk0 ;  //  Posedge  at  T : 5  ,  15  ,  25  ,  35  ,  45  etc ..

  bit  clk1 ;

 initial  begin
   forever  begin         //  Clock  with  40%  Duty  Cycle  !!
     #6  clk1 = ! clk1 ;  //  Posedge  at  T : 6  ,  16  ,  26  ,  36  ,  46  etc ...
     #4  clk1 = ! clk1 ;  //  Negedge  at  T : 10  ,  20 ,  30  ,  40  ,  50  etc ...
   end 
 end 

 bit  A  ,  B  ;

 sequence  mclocks ; // Could be declared as property as well !!
   @( posedge clk0 )  A   ##2  @( posedge clk1 )   ( B , $display("TIME : %2t  B  is  True " , $time ) ) ; 
 endsequence

 assert property ( mclocks ) ;

 initial  begin
  #4 ; A = 1 ;
       B = 1 ;
  #25 ; $finish() ;
 end
endmodule


Is ##N considered legal ? ( where N is elaboration-time constant and N > 1 )
( On trying the same on the licensed simulators at work only 1 out of 3 tools considers it as legal )

Two tools throw Compilation Error irrespective of whether mclocks is declared as sequence / property .

In reply to MICRO_91:
16.13.1 Multiclocked sequences (Page 447)
Differently clocked or multiclocked sequence operands cannot be combined with any sequence operators other than ##1 and ##0. For example, if clk1 and clk2 are not identical, then the following are illegal:
@(posedge clk1) s1 ##2 @(posedge clk2) s2
@(posedge clk1) s1 intersect @(posedge clk2) s2

Ben Cohen
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In reply to ben@SystemVerilog.us:

Thanks Ben .
I have one last question regarding the definition for ’ identical ’ :

if clk1 and clk2 are not identical

If I were to write :


  bit  clk0  ;
  always  #5  clk0  =  !clk0 ;

  bit  clk1  ;
  always  #5  clk1  =  !clk1 ;

 sequence  mclocks ; // Could be declared as property as well !!
   @(posedge clk0)  A  ##2 @( posedge clk1 ) ( B , $display("TIME : %2t  B  is  True " , $time ) ) ; 
 endsequence

Even though clk0 and clk1 are in-phase and of the same period , clk0 and clk1 isn’t considered identical and I still observe compilation error .

The only way ##2 would work if it was a single clock in picture , right ? :


sequence  mclocks ; // Could be declared as property as well !!
   @( posedge clk0 ) A  ##2  @( posedge clk0 ) ( B , $display("TIME : %2t  B  is  True " , $time ) ) ; 
 endsequence

In reply to MICRO_91:

You are correct, the ##2 would only work in a singly clocked design.
One would think that 1800’s interpretation of "For example, if clk1 and clk2 are not identical /b] would mean that if clk1 is assigned to clk0 they are identical. Something like:
always #5 clk0 = ! clk0 ;
always clk1=clk0; // identical clock??? Interpreted as NOT IDENTICAL by tools
[b]HOWEVER
, this is NOT what tools are interpreting. Tools interpret clk1 as different as clk0. I doubt that this interpretation will change, meaning that under NO circumstances you can use in multiclocking anything but the following constructs


@(posedge clk0 seq1 ##0 @(posedge clk1) seq2; // LEGAL 
@(posedge clk0 seq1 ##1 @(posedge clk1) seq2; // LEGAL 
@(posedge clk0 seq1 |->  @(posedge clk1) seq2; // LEGAL 
@(posedge clk0 seq1 |=>  @(posedge clk1) seq2; // LEGAL