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  • Is ##2 legal within a sequence or property expression ?

Is ##2 legal within a sequence or property expression ?

SystemVerilog 6745
Is ##2 legal within a... 1
MICRO_91
MICRO_91
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235 posts
May 15, 2023 at 6:10 am

Hi ,
Generally I observe ##1 used between sequences within a property or sequence expression .
I was curious whether ##N is legal ? ( where N is elaboration-time constant and N > 1 )

module  top;
 
  bit  clk0  ;
 
  always  #5  clk0  =  ! clk0 ;  //  Posedge  at  T : 5  ,  15  ,  25  ,  35  ,  45  etc ..
 
  bit  clk1 ;
 
 initial  begin
   forever  begin         //  Clock  with  40%  Duty  Cycle  !!
     #6  clk1 = ! clk1 ;  //  Posedge  at  T : 6  ,  16  ,  26  ,  36  ,  46  etc ...
     #4  clk1 = ! clk1 ;  //  Negedge  at  T : 10  ,  20 ,  30  ,  40  ,  50  etc ...
   end 
 end 
 
 bit  A  ,  B  ;
 
 sequence  mclocks ; // Could be declared as property as well !!
   @( posedge clk0 )  A   ##2  @( posedge clk1 )   ( B , $display("TIME : %2t  B  is  True " , $time ) ) ; 
 endsequence
 
 assert property ( mclocks ) ;
 
 initial  begin
  #4 ; A = 1 ;
       B = 1 ;
  #25 ; $finish() ;
 end
endmodule

Is ##N considered legal ? ( where N is elaboration-time constant and N > 1 )
( On trying the same on the licensed simulators at work only 1 out of 3 tools considers it as legal )

Two tools throw Compilation Error irrespective of whether mclocks is declared as sequence / property .

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ben@SystemVerilog.us
ben@SystemVerilog.us
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2883 posts
May 15, 2023 at 9:17 am

In reply to MICRO_91:
16.13.1 Multiclocked sequences (Page 447)
Differently clocked or multiclocked sequence operands cannot be combined with any sequence operators other than ##1 and ##0. For example, if clk1 and clk2 are not identical, then the following are illegal:
@(posedge clk1) s1 ##2 @(posedge clk2) s2
@(posedge clk1) s1 intersect @(posedge clk2) s2

Ben Cohen

Link to the list of papers and books that I wrote, many are now donated.
http://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf
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https://rb.gy/f3zhhmysig

MICRO_91
MICRO_91
Full Access
235 posts
May 15, 2023 at 12:03 pm

In reply to ben@SystemVerilog.us:

Thanks Ben .
I have one last question regarding the definition for ' identical ' :

Quote:
if clk1 and clk2 are not identical

If I were to write :

  bit  clk0  ;
  always  #5  clk0  =  !clk0 ;
 
  bit  clk1  ;
  always  #5  clk1  =  !clk1 ;
 
 sequence  mclocks ; // Could be declared as property as well !!
   @(posedge clk0)  A  ##2 @( posedge clk1 ) ( B , $display("TIME : %2t  B  is  True " , $time ) ) ; 
 endsequence

Even though clk0 and clk1 are in-phase and of the same period , clk0 and clk1 isn't considered identical and I still observe compilation error .

The only way ##2 would work if it was a single clock in picture , right ? :

sequence  mclocks ; // Could be declared as property as well !!
   @( posedge clk0 ) A  ##2  @( posedge clk0 ) ( B , $display("TIME : %2t  B  is  True " , $time ) ) ; 
 endsequence
ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2883 posts
May 15, 2023 at 12:49 pm

In reply to MICRO_91:

You are correct, the ##2 would only work in a singly clocked design.
One would think that 1800's interpretation of "For example, if clk1 and clk2 are not identical /b] would mean that if clk1 is assigned to clk0 they are identical. Something like:
always #5 clk0 = ! clk0 ;
always clk1=clk0; // identical clock??? Interpreted as NOT IDENTICAL by tools
[b]HOWEVER
, this is NOT what tools are interpreting. Tools interpret clk1 as different as clk0. I doubt that this interpretation will change, meaning that under NO circumstances you can use in multiclocking anything but the following constructs

@(posedge clk0 seq1 ##0 @(posedge clk1) seq2; // LEGAL 
@(posedge clk0 seq1 ##1 @(posedge clk1) seq2; // LEGAL 
@(posedge clk0 seq1 |->  @(posedge clk1) seq2; // LEGAL 
@(posedge clk0 seq1 |=>  @(posedge clk1) seq2; // LEGAL 
MICRO_91
MICRO_91
Full Access
235 posts
September 02, 2023 at 1:15 am

A quick addition to the thread :
(a) LRM 16.13.1 Multiclocked sequences :

@(posedge clk0) sig0 ##1 @(posedge clk1) sig1
 
If clk0 and clk1 are not identical, then the clocking event for the sequence changes after ##1. 
If clk0 and clk1 are identical, then the clocking event does not change after ##1, and the preceding sequence is equivalent to the singly clocked sequence.
 
@(posedge clk0) sig0 ##1 sig1

(b) LRM 16.16.1 Semantic leading clocks for multiclocked sequences and properties :

A multiclocked property has a unique semantic leading clock in cases where all its leading clocks are identical.
 
wire clk1, clk2;
logic a, b;
...
assign clk2 = clk1; // Both clocks are of same period and always in-phase
 
a1: assert property (@(clk1) a and @(clk2) b); // Illegal
 
Though both clocks of a1 have the same value, they are not identical. Therefore, a1 does not have a unique semantic leading clock.

So as soon as we declare 2 different variables eg. clk0 and clk1 , they are essentially non-identical irrespective of their period and phase

Have_A_Doubt
Have_A_Doubt
Forum Access
225 posts
September 02, 2023 at 3:02 am

In reply to ben@SystemVerilog.us:

Hi Ben ,

Quote:
16.13.1 Multiclocked sequences (Page 447)
Differently clocked or multiclocked sequence operands cannot be combined with any sequence operators other than ##1 and ##0. For example, if clk1 and clk2 are not identical, then the following are illegal:
@(posedge clk1) s1 ##2 @(posedge clk2) s2
@(posedge clk1) s1 intersect @(posedge clk2) s2

This quote is specifically for a multiclocked sequence :

sequence  mclocks_seq; 
   @(posedge clk0) a ##2  @(posedge clk1) B ;  // This is a sequence_expression as property_expression is invalid within a sequence body
 endsequence
 assert property ( mclocks_seq ) ;

However if I were to declare 'mclocks_seq' as property , I observe it's also invalid

property  mclocks_prop; 
  @(posedge clk0) a ##2  @(posedge clk1) B ;  // This is a property_expression
 endproperty
 assert property ( mclocks_prop ) ;

I went through LRM for this and I noted the following . Please correct me if wrong :

(1) Syntax 16-16—Property construct syntax :

       property_expr ::=
              sequence_expr
 

[Q1]This means all sequence_expressions are implicitly property_expressions , right ?

(2) 16.13.1 Multiclocked sequences :

 If s1, s2 are sequence expressions with no clocking events, then the multiclocked sequence
 
  @(posedge clk1) s1 ##1 @(posedge clk2) s2
 
 is legal only if neither s1 nor s2 can match the empty word. 
 

(3) 16.13.2 Multiclocked properties :

    Multiclocked sequences are themselves multiclocked properties. For example:
 
      @(posedge clk0) sig0 ##1 @(posedge clk1) sig1
 
 is a multiclocked property. If a multiclocked sequence is evaluated as a property starting at some point, the
evaluation returns true if, and only if, there is a match of the multiclocked sequence beginning at that point.
 

Via (2) and (3) :
@(posedge clk1) s1 ##1 @(posedge clk2) s2

This is a multiclocked sequence .
Since a sequence is also a property , it can also be said that it's a multiclocked property

Hence when 16.13.1 Multiclocked sequences says that :

Differently clocked or multiclocked sequence operands cannot be combined with any sequence operators other than ##1 and ##0. 
For example, if clk1 and clk2 are not identical, then the following are illegal:
 
@(posedge clk1) s1 ##2 @(posedge clk2) s2 

So to summarize :

  • Sequence concatenation operator '##' is used between two sequence_expressions. It doesn't apply for only a sequence,it could be applied between 2 property_expression as well ( as a sequence_expr is also a property_expr by default )
  • A multiclocked sequence has clocking event Eg. @( posedge clk1 ) / @( posedge clk2 ) at the start of the sequence_expression.
  • Via (1) since a sequence_expression is also a property_expression , ##2 is illegal even for a property_expression

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2883 posts
September 02, 2023 at 10:10 am

In reply to Have_A_Doubt:

Quote:
In reply to ben@SystemVerilog.us:

Hi Ben ,

Quote:
16.13.1 Multiclocked sequences (Page 447)
Differently clocked or multiclocked sequence operands cannot be combined with any sequence operators other than ##1 and ##0. For example, if clk1 and clk2 are not identical, then the following are illegal:
@(posedge clk1) s1 ##2 @(posedge clk2) s2
@(posedge clk1) s1 intersect @(posedge clk2) s2

This quote is specifically for a multiclocked sequence :

sequence  mclocks_seq; 
   @(posedge clk0) a ##2  @(posedge clk1) B ;  // This is a sequence_expression as property_expression is invalid within a sequence body
 endsequence
 assert property ( mclocks_seq ) ;

However if I were to declare 'mclocks_seq' as property , I observe it's also invalid

property  mclocks_prop; 
  @(posedge clk0) a ##2  @(posedge clk1) B ;  // This is a property_expression
 endproperty
 assert property ( mclocks_prop ) ;

I went through LRM for this and I noted the following . Please correct me if wrong :

(1) Syntax 16-16—Property construct syntax :

       property_expr ::=
              sequence_expr
 

[Q1]This means all sequence_expressions are implicitly property_expressions , right ?


1) see https://verificationacademy.com/forums/systemverilog/sva-multiple-clocks#reply-115237
2) If I define a sequence in a declaration, that sequence is considered a sequence that can be used as a property. 1800 defines that multiclocking in a sequence declaration is illegal. You can declare that sequence in a property declaration, but to use it, you need a Leading Clocking Event (LCE). You can use the content of that sequence in a consequent which is a property. You cannot use it in an antecedent.
Quote:

(2) 16.13.1 Multiclocked sequences :

 If s1, s2 are sequence expressions with no clocking events, then the multiclocked sequence
 
  @(posedge clk1) s1 ##1 @(posedge clk2) s2
 
 is legal only if neither s1 nor s2 can match the empty word. 
 

(3) 16.13.2 Multiclocked properties :

    Multiclocked sequences are themselves multiclocked properties. For example:
 
      @(posedge clk0) sig0 ##1 @(posedge clk1) sig1
 
 is a multiclocked property. If a multiclocked sequence is evaluated as a property starting at some point, the
evaluation returns true if, and only if, there is a match of the multiclocked sequence beginning at that point.
 

Via (2) and (3) :
@(posedge clk1) s1 ##1 @(posedge clk2) s2

This is a multiclocked sequence .
Since a sequence is also a property , it can also be said that it's a multiclocked property


You'tr making it too complicated. A sequence can be interpreted as a sequence or as a property depending where it is used.
Quote:

Hence when 16.13.1 Multiclocked sequences says that :
Differently clocked or multiclocked sequence operands cannot be combined with any sequence operators other than ##1 and ##0. 
For example, if clk1 and clk2 are not identical, then the following are illegal:
 
@(posedge clk1) s1 ##2 @(posedge clk2) s2 

So to summarize :

  • Sequence concatenation operator '##' is used between two sequence_expressions. It doesn't apply for only a sequence,it could be applied between 2 property_expression as well ( as a sequence_expr is also a property_expr by default )

NO. (sq ##1 s2) is legal, and is a sequence interpreted as a property if a consequent.
The ## is a sequence operator.
(a|-> b) ##1 (c |-> d) // is illegal, the ## is not a property operator. 
(a|-> b) implies (c |-> d) //is legal, the implies is a property operator, not same as ##

  • A multiclocked sequence has clocking event Eg. @( posedge clk1 ) / @( posedge clk2 ) at the start of the sequence_expression.
  • Via (1) since a sequence_expression is also a property_expression , ##2 is illegal even for a property_expression

  • I see the ##0, |->, ##1, |=> as clock switch operators. 
    ##0, |-> switch a LHS sequence to the RHS sequence on the nearest RHS clocking event.
    @(posedge clk1) s1 |-> @(posedge clk2 s2). 
    If clk1 and clk2 occur in the same time step, e.g., at t10, then s2 start evaluating at t10
    If clk1  occurs at t10 but clk2 occurs at t17, then s2 start evaluating at t17
     
    @(posedge clk1) s1 |=> @(posedge clk2 s2). 
    If clk1 and clk2 occur in the same time step and clk1  occurs at t10 but clk2 occurs at t10, t17, t23, then s2 start evaluating at t17
     
    If clk1 occur at t10 but but clk2 occurs at t17, then s2 start evaluating at t17
    Have_A_Doubt
    Have_A_Doubt
    Forum Access
    225 posts
    September 05, 2023 at 10:37 am

    In reply to ben@SystemVerilog.us:

    Hi Ben,

    Quote:
    A sequence can be interpreted as a sequence or as a property depending where it is used.

    I am trying scenarios on how a sequence is recognized as sequence or property.
    Consider the sequence expression : @(posedge clk0) a ##1 @(posedge clk1) b

    Examples on a sequence being interpreted as sequence expression :

    1. Sequence is directly part of assert property assert property( @(posedge clk0) a ##1 @(posedge clk1) b );

    2. Sequence is part of sequence body :
           sequence seq; // Valid as both antecedent and consequent
            @(posedge clk0) a ##1 @(posedge clk1) b;
           endsequence
       

    Examples on a sequence being interpreted as property expression :

    1. Sequence is part of property body :
           property prop;  //  Valid as consequent OR  assert property ( prop );
            @(posedge clk0) a ##1 @(posedge clk1) b;
           endproperty
       

    2. Sequence is written in consequent within assert property :
          assert property( @posedge clk2) d |=>  @(posedge clk0) a ##1 @(posedge clk1) b );
       

    Have I got it right ? Have I missed out on any more possible examples ?

    ben@SystemVerilog.us
    ben@SystemVerilog.us
    Full Access
    2883 posts
    September 05, 2023 at 11:03 am

    In reply to Have_A_Doubt:

    Why are you so concerned as to how it is interpreted?
    A sequence can be interpreted as a sequence or as a property depending where it is used.
    1800 specifies that a property is defined by several options.
    16.12 Declaring properties

    property_expr ::= 
      sequence_expr 
    | strong ( sequence_expr )
    | weak ( sequence_expr ) 
    | ( property_expr ) 
    | not property_expr 
    | property_expr or property_expr 
    | property_expr and property_expr
    ...
    Thus,
    assert property( @(posedge clk0) a ##1 @(posedge clk1) b );
    What's inside is whatever a property is allowed to be, and that can be anything that is allowed in 1800 16.12 Declaring properties; thus, assert property(a_propetry_as_define_in_1800).
    It really is that simple!
    Ben
    Have_A_Doubt
    Have_A_Doubt
    Forum Access
    225 posts
    September 05, 2023 at 12:11 pm

    In reply to ben@SystemVerilog.us:

    Quote:
    Why are you so concerned as to how it is interpreted?

    It was related to the sva-multiple-clocks you shared above.

    As discussed in the thread , for multi-clocking to be legal it should be interpreted as property expression

    ben@SystemVerilog.us
    ben@SystemVerilog.us
    Full Access
    2883 posts
    September 05, 2023 at 3:10 pm

    In reply to Have_A_Doubt:

    Every property in an assertion needs a leading clocking event (LCE).

    let e1=posedge clk1;
    let e2=posedge clk2;
    @(e1) a_seq1 ##1 @(e2) a_seq2  // can be a sequence used as an antecedent or in a property
    // It has a LCE
    @(e1) a_seq1 and @(e2) a_seq2 // must be used in a property that contains a LCE.
     
    @(e1) a |-> @(e1) a_seq1 and @(e2) a_seq2 ; // OK 
    not(@(e1) a_seq1 and @(e2) a_seq2);  // no LCE
     
     bit clk1, clk2;
      sequence s1a; @(posedge clk1) a ##1 @(posedge clk2) b; endsequence
      sequence s1b; @(posedge clk1) a and  @(posedge clk2) b; endsequence // 44
      assert property(@(posedge clk1) 1 ##0 s1b);  //45
    ** Warning: testbench.sv(44): (vlog-2047) Sequence/SERE 's1b' declared in 'YourModule' has multiple leading clocks. Such
    sequence/SERE cannot be instanced as maximal property of a directive.
    ** Error: testbench.sv(45): (vlog-2049) Directive 'assert__0' has property instances with multiple leading clocks.
    Please fix the clocking issues
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