Hi,
Can any please tell me what is the best method to verify a 16 bit RISC processor? I have a 16bit processor based on SPARC platform with 4 stage pipeline to verify. I am thinking of developing a reference model for the same but dont know the blocks to add in golden model(eg. pipeline?) . What is the best strategy here. What about the test inputs? Directed (memory image of assembly programs) or constrained random?
thanks in advance