So I’m on HDLBits trying to work out a problem for a 12 hour clock. I’ve tried it two different ways by now. First I’ve tried it with conditional statements, and the second way I tried it with case statements. The first time, I’m getting and issue that there are some mismatches for my Seconds and Minutes outputs and its also saying that the code can not simulate. When I do it with the case statements, I’m not getting any mismatches, but again it is not simulating. With the case statement version, its saying that there is an iteration limit @ time 0 ps, while for the conditional version, its saying that there is an iteration limit @ time 38255 ps. Do I have a loop somewhere that I’m not seeing? I will attach both files so you can see the code. This is the link to the problem in question Count clock - HDLBits
With Conditional Statements
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [3:0] h1, h2, m1, m2, s1, s2;
reg one, two, three, four, five;
always @ (posedge clk)
s1 <= reset ? 4'h0 : ( ena ? (reset || s1 == 9 ? 4'h0 : s1 + 1) : s1);
assign one = (s1 == 9) ? 1 : 0;
always @ (posedge clk)
s2 <= reset ? 4'h0 : ( one ? (reset || s2 == 5 ? 4'h0 : s2 + 1) : s2);
assign two = (s1 == 9) && (s2 == 5) ? 1 : 0;
always @ (posedge clk)
m1 <= reset ? 4'h0 : ( two ? (reset || m1 == 9 ? 4'h0 : m1 + 1) : m1);
assign three = (m1 == 9) && (s1 == 9) && (s2 == 5) ? 1 : 0;
always @ (posedge clk)
m2 <= reset ? 4'h0 : ( three ? (reset || m2 == 5 ? 4'h0 : m2 + 1) : m2);
assign four = (m2 == 5) && (m1 == 9) && (s1 == 9) && (s2 == 5) ? 1 : 0;
always @ (posedge clk)begin
if(reset)begin
h1 <= 4'h2;
h2 <= 4'h1;
end else begin
if(four & reset)begin
h1 <= 4'h2;
h2 <= 4'h1;
end else if(four & ~reset) begin
if(h2 == 4'h1 && h1 == 4'h2)begin
h2 <= 4'h0;
h1 <= 4'h1;
end else if(h2 == 4'h1 && h1 != 4'h2)begin
h1 <= h1 + 1;
end else if(h2 != 4'h1 && h1 != 4'h9)begin
h1 <= h1 + 1;
end else if(h2 == 4'h0 && h1 == 4'h9)begin
h1 <= 4'h0;
h2 <= 4'h1;
end
end
end
end
assign hh = {h2, h1};
assign mm = {m2, m1};
assign ss = {s2, s1};
assign pm = reset ? 0 : ( hh == 8'h12 && mm == 8'h59 && ss == 8'h59) ? ~pm : pm;
endmodule
With Case Statements
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
reg [7:0] h1, h2, m1, m2, s1, s2;
reg one, two, three, four;
assign #1 h1 = h2;
assign #1 m1 = m2;
assign #1 s1 = s2;
twelve z1(h1, h2);
sixty z2(m1, m2);
sixty z3(s1, s2);
always @ (posedge clk)begin
#1 ss <= reset ? 8'h00 : ( ena ? (reset ? 8'h00 : s2) : s2);
#1 mm <= reset ? 8'h00 : ( s2 == 8'h59 ? (reset ? 8'h00 : m2) : m2);
#1 hh <= reset ? 8'h12 : ( (s2 == 8'h59) && (m2 == 8'h59) ? (reset ? 8'h12 : h2) : h2);
end
assign #1 pm = reset ? 0 : ( hh == 8'h11 && mm == 8'h59 && ss == 8'h59) ? ~pm : pm;
endmodule
module sixty(input reg [7:0]a, output reg [7:0]b);
always @ (*)begin
case(a)
8'h00 : b <= 8'h01;
8'h01 : b <= 8'h02;
8'h02 : b <= 8'h03;
8'h03 : b <= 8'h04;
8'h04 : b <= 8'h05;
8'h05 : b <= 8'h06;
8'h06 : b <= 8'h07;
8'h07 : b <= 8'h08;
8'h08 : b <= 8'h09;
8'h09 : b <= 8'h10;
8'h10 : b <= 8'h11;
8'h11 : b <= 8'h12;
8'h12 : b <= 8'h13;
8'h13 : b <= 8'h14;
8'h14 : b <= 8'h15;
8'h15 : b <= 8'h16;
8'h16 : b <= 8'h17;
8'h17 : b <= 8'h18;
8'h18 : b <= 8'h19;
8'h19 : b <= 8'h20;
8'h20 : b <= 8'h21;
8'h21 : b <= 8'h22;
8'h22 : b <= 8'h23;
8'h23 : b <= 8'h24;
8'h24 : b <= 8'h25;
8'h25 : b <= 8'h26;
8'h26 : b <= 8'h27;
8'h27 : b <= 8'h28;
8'h28 : b <= 8'h29;
8'h29 : b <= 8'h30;
8'h30 : b <= 8'h31;
8'h31 : b <= 8'h32;
8'h32 : b <= 8'h33;
8'h33 : b <= 8'h34;
8'h34 : b <= 8'h35;
8'h35 : b <= 8'h36;
8'h36 : b <= 8'h37;
8'h37 : b <= 8'h38;
8'h38 : b <= 8'h39;
8'h39 : b <= 8'h40;
8'h40 : b <= 8'h41;
8'h41 : b <= 8'h42;
8'h42 : b <= 8'h43;
8'h43 : b <= 8'h44;
8'h44 : b <= 8'h45;
8'h45 : b <= 8'h46;
8'h46 : b <= 8'h47;
8'h47 : b <= 8'h48;
8'h48 : b <= 8'h49;
8'h49 : b <= 8'h50;
8'h50 : b <= 8'h51;
8'h51 : b <= 8'h52;
8'h52 : b <= 8'h53;
8'h53 : b <= 8'h54;
8'h54 : b <= 8'h55;
8'h55 : b <= 8'h56;
8'h56 : b <= 8'h57;
8'h57 : b <= 8'h58;
8'h58 : b <= 8'h59;
8'h59 : b <= 8'h00;
endcase
end
endmodule
module twelve(input reg [7:0]a, output reg [7:0]b);
always @ (*)begin
case(a)
8'h00 : b <= 8'h01;
8'h01 : b <= 8'h02;
8'h02 : b <= 8'h03;
8'h03 : b <= 8'h04;
8'h04 : b <= 8'h05;
8'h05 : b <= 8'h06;
8'h06 : b <= 8'h07;
8'h07 : b <= 8'h08;
8'h08 : b <= 8'h09;
8'h09 : b <= 8'h10;
8'h10 : b <= 8'h11;
8'h11 : b <= 8'h12;
8'h12 : b <= 8'h00;
endcase
end
endmodule