[->1] and [=1]

SystemVerilog
1

In many cases “[->1]” is used to end the assertion. Can this be replaced with “[=1]”?
What is that “[->1]” adding extra to the assertion?

req |=> !req throughout ack[->1]

2

In reply to yourcheers:

See Difference between goto and non-consecutive repetition assertion | Verification Academy