#0 delays in systemverilog

SystemVerilog
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1

Hi,

Do we use #0 delays in system verilog ?
If yes where do we use it ?
What are the advantages and disadvantages of using them ?

2

In reply to Ravi007:

You do not want to use #0 delays. You don’t want to use them for the very reason you are asking–people have no idea what they do and it causes more problems than people think they solve.

3

In reply to Ravi007:

Hi,
Do we use #0 delays in system verilog ?

We generally don’t use #0 delays in SystemVerilog.

If yes where do we use it ?

Some people may suggest it’s usage in differed assertions but that itself is questionable.

What are the advantages and disadvantages of using them ?

A statement such as #0 x = y, is an example of an inactive event is an explicit zero-delay assignment. It occurs at the current simulation time but is processed after all active events at the current simulation time have been processed.
Using #0 delay if you are designing, itself makes your code non-synthesizable.

All in all, #0 delays should not be used. As it raises more questions in a code than solving it.