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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
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    • Pattern Resources

      • Start Here - Patterns Library Overview
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
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      • Package/Organization
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      • SystemVerilog Guidelines
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • VA Live - Multiple Dates & Locations
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      • SystemVerilog Assertions
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      • Avery & Siemens VIP
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      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
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    • Conferences & WRG

      • 2022 Functional Verification Study
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    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

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OVM
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Forums: OVM

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2421 questions in OVM

  • TITLE
    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • run() task in scoreboard
    1  
    5,964  
    14 years 4 months ago
    by saurabh jain  
    14 years 4 months ago
    by kinjalshah  
  • Sequence Override by using set_type_override_by_name call
    4  
    1,241  
    3 years 6 months ago
    by Arun_Rajha  
    3 years 6 months ago
    by Arun_Rajha  
  • can we use $rose for multibits
    6  
    2,200  
    3 years 7 months ago
    by vickyvinay  
    3 years 7 months ago
    by vickyvinay  
  • can use case statement inside if else block
    2  
    987  
    3 years 7 months ago
    by vickyvinay  
    3 years 7 months ago
    by vickyvinay  
  • counter for write response
    1  
    987  
    3 years 7 months ago
    by vickyvinay  
    3 years 7 months ago
    by chr_sue  
  • Error-[ICTTFC] Incompatible complex type usage
    2  
    2,306  
    3 years 7 months ago
    by muthuven  
    3 years 7 months ago
    by muthuven  
  • Difference between get() and get_next_item()?
    6  
    13,953  
    13 years 6 months ago
    by vivekm  
    3 years 7 months ago
    by UVM_learner6  
  • Regarding the report macro - OVM_FATAL
    1  
    997  
    3 years 8 months ago
    by Basu  
    3 years 8 months ago
    by dave_59  
  • Difference Between Virtual and Pure Virtual
    2  
    28,095  
    15 years 3 months ago
    by kunal_1514  
    3 years 8 months ago
    by JA  
  • global_stop_request() & $finish
    17  
    16,726  
    14 years 4 days ago
    by chip_maker  
    13 years 11 months ago
    by sdonofrio  
  • OVM_ERROR @ 0: reporter [FLDTNC] struct is 8800 bits; maximum field size is 4096, truncating
    1  
    856  
    3 years 10 months ago
    by nanda521  
    3 years 10 months ago
    by dave_59  
  • Why `ifndef and `define are used together?
    13  
    27,703  
    10 years 4 months ago
    by xierian  
    3 years 10 months ago
    by J_M  
  • Why the task body() inside sequence is of type virtual??
    13  
    14,464  
    12 years 8 months ago
    by desperado  
    4 years 2 weeks ago
    by sriram.seshagiri  
  • Properties encapsulation
    2  
    1,347  
    4 years 1 month ago
    by hamza  
    4 years 1 month ago
    by hamza  
  • How to manage the seed of randomization?
    9  
    33,331  
    14 years 11 months ago
    by ahan  
    4 years 2 months ago
    by JA  
  • OVM wrapper for Verilog Bfms??
    26  
    22,233  
    15 years 3 months ago
    by anantv  
    4 years 3 months ago
    by rthakur1  
  • cosimulate SystemVerilog and python
    8  
    21,979  
    15 years 2 months ago
    by pieter  
    5 years 8 months ago
    by dave_59  
  • Multiple sequencers to the same driver
    9  
    7,558  
    14 years 5 months ago
    by asharai  
    14 years 4 months ago
    by Ritesh  
  • enumeration error in systemverilog
    9  
    15,527  
    13 years 2 months ago
    by kaes  
    13 years 2 months ago
    by Vaibhav Tekale  
  • Why is SUPER.body() used in a task in the child sequence which is derived from a parent sequence? The parent sequence the task is not mentioned to be of virtual type
    1  
    3,939  
    4 years 6 months ago
    by shruti_k  
    4 years 6 months ago
    by cgales  

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16,361 Questions

49,254 Replies

87,505 Users

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