White box testing - access to internal signals

OVM
1

How do I setup a virtual interface for signals that are not i/o to the DUT?

2

You can assign an internal signal to the interface with a hierachical path, eg:

assign u_interface.AA = $root.u_a.u_sub_a.signal_b;

where u_interface is the interface instance which your virtual interface point to.
3

We use the below example in some of our advanced SV training sessions/bootcamps. Crux of it is to use SVA’s “bind” feature and have the interface use all signals required as port level signals. Its a demo code showing how to write SVA on those internal signals. Doing a virtual interface say through a uvm_config_db::set() is a natural extension. Do let me know if you need assistance in that.

HTH
Ajeetha, CVC



  import uvm_pkg::*;
  `include "uvm_macros.svh"

interface mon_if (input logic clk, int_sig1, int_sig2);
  
  a_sig1_then_sig2 : assert property ( @(posedge clk)
    int_sig1 |=> int_sig2) else
    `uvm_error ("SVA", "int_sig2 didn't follow int_sig1"); 

endinterface : mon_if

module m;
  logic clk, int_sig1, int_sig2;
  initial begin : clk_gen
    clk <= 1'b0;
    forever #10 clk <= !clk;
  end : clk_gen
  default clocking @ (posedge clk);
  endclocking
  initial begin : test
    int_sig1 <= 1'b0;
    int_sig2 <= 1'b0;
    ##10;
    int_sig1 <= 1'b1;
    ##1;
    int_sig1 <= 1'b0;
    ##10;
    $finish;    
  end : test
endmodule : m

bind m mon_if mon_if_0 (.*);

Here is a sample output from a Questa run:

** Error: int_sig2 didn’t follow int_sig1

Time: 230 ns Started: 210 ns Scope: m.mon_if_0.a_sig1_then_sig2 File: …/if_with_int_sigs.sv Line: 10

4

In reply to ajeetha:

My DVCon 2102 paper has some examples of this.

https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection

5

In reply to dave_59:

Those examples are so confusing! is there something simple like the VHDL alias function?

6

In reply to dave_59:

To monitor internal signals this worked more me in the test bench:
For example monitoring a control signal inside module_ints2 when you have
UUT [ module_ints [ module_ints ] ].

You need an alias to assign to the internal signal like this:

logic _internal_signal
assign _internal_signal = [net path]

The net path is test_bench_name.module_inst1.module_inst2.internal_signal

You can find the net path if you can navigate to the net in the objects window of ModelSim, then right click and select copy. Then paste the tcl path into your test bench. Then replace the “/” by .

The binding concept had me for a spin for days, and it still doesn’t work.