HI All,
I don’t know what end_of_elaboration and start_of_simulation for.
Do these two phase have some specific purpose?
Thank you!
Hi Ahan,
These phases originate in the SystemC world, so to give you a better idea of their purpose, let me quote from the SystemC LRM since the concepts still apply.
end_of_elaboration (note that SystemC “modules” are the equivalent of OVM component classes):
allow an application to perform housekeeping actions at the end of elaboration that do not need to modify the module hierarchy. Examples include design rule checking, actions that depend on the number of times a port is bound, and printing diagnostic messages concerning the module hierarchy
start_of_simulation:
allow an application to perform housekeeping actions at the start of simulation. Examples include opening stimulus and response files and printing diagnostic messages
Hope that makes it clearer.
Regards
Dave
Hi Dave,
Thanks for your information.
Since OVM is based on SV,what we should consider the SC TLM concept?
Thank you!
Hi Ahan,
Since OVM is based on SV,what we should consider the SC TLM concept?
Because OVM uses the SystemC TLM 1.0 as its communication mechanism. Here is another quote for you, this time from the OVM white paper available on this web site:
Under the OVM, communication among VIP and testbench components uses a SystemVerilog implementation of the widely adopted transaction-level modeling (TLM) standard originally developed by the Open SystemC Initiative (OSCI). In addition to fostering interoperability among SystemVerilog components, the choice of TLM makes it easy to integrate verification components written in other languages, such as e and SystemC
In other words, adding SystemC-compatible phases into OVM simplifies interaction between SystemC models and the SV OVM environment in a mixed language testbench.
Regards,
Dave
Hi Dave,
You give me a exact backgroud of OVM and the reason why we adopt SC TLM in OVM.
Thank you very much for your great help!