Want to have display with TESTPASSED/FAILED kind of messages in my testbench environment

OVM
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1

Hi,

I want to get TEST PASSED/FAILED display’s when i run particular testcase.How to get it them displayed.

Where should i add logic for this.

Thanks

2

A very common question, see a scale-able solution at Verification Course Blog | VeriLog Courses | CVC

You can add that to your env/base_test.

However remember that this doesn’t capture errors emerging from RTL code itself (if designers have added some $display (“Error”) sort of code). Other common mistake is not to add `uvm_error in SVA action blocks. So to summarize - if UVM says “FAIL” it is FAIL, but if it says PASS - it may not be fully true, consult your full log file.

HTH
Ajeetha, CVC

3

If you are using Questa its Verification Management features, It records the most severe message as part of the UCIS TESTSTATUS attribute, so even if the UVM passes, but there are things like assertion errors, the TESTSTATUS will be set to ERROR.