Urgent Help: Connecting VHDL port with SV Interface?

OVM
1

Hi All,

Doubt is connect a VHDL DUT With an SV Interface!!!

This is first declaration of a signal in vhdl like below::

type t_ar7_0 is array (natural range<>) of std_logic_vector(7 downto 0);

This they have used to create a packed dimensional in vhdl for a port signal in the top module as given below::

ABC_MMM : out t_ar7_0(1 to 8);

So its like 7 to 0 of 1 to 8 signal in vhdl…

Now I had declared a counter part in interface to connect this module as logic [1:8] [7:0] abc_mmm;

Now, in a module how to connect these two signals, I tried like this but its giving illegal port connect for VHDL type.

// DUT instance
ABC abc_dut (.ABC_MMM(interface.abc_mmm));

How can i Connect a sort of array port declaration in VHDL with SV interface!!!
Quite urgent help out plz…

Thanks,
Desperado

2

I think your interface declaration of abc_mmm is incorrect. Try:

logic [7:0] abc_mmm[1:8];

I think this will match the VHDL declaration.

3

Hi All,

Added with the above question,

i tried running the same in Questa, it was giving error as

illegal port connect with vhdl and verilog

when tried running the same with cadence irun, it was working fine and the 2-dimensional port connection in the port got connected…

Kindly help me out regarding the same, a request to Mentor GUyrs, whether is it tool issue or not supported feature, kndly help me out, case is quite critical…

Thanks,

Desperado

4

Which version doesn’t work in Questa? The solution I posted above works with Questa. Did you try it?

5

Hi Gales,

I tried the same and as well all the possible ways, but its not working.
Oly possiblity is to create a wrapper around the same, but the other tool is working fine.

** Fatal: (vsim-3362) The type of VHDL port ‘ABC_MMM’ is invalid for Verilog connection (7th connection).

I am using Questa Sim 6.6C .

Can you kindly guide me out of this situation, quite critical.

Thanks,
Desperado

6

Desperado,

Just because you think something is working in another tool, and not another, does not always mean one tool is right and the other tool is wrong. In this case, there is no standard definition for VHDL/SystemVerilog interoperability. Given that SystemVerilog considers unpacked types as a strong type (i.e. no implicit casting) and all types in VHDL are a strong type, I believe Questa’s interpretation is valid, and the connection you are trying to make is invalid.

Dave

7

Hi Dave,

Thanks for your clear explanation. But can you kindly give me an work around for the same, how can i easily connect the same, as I am having such type of connections for numerous signals. So is it the wrapper the only way to connect ? Or any quick workaround.

Kindly suggest and help out.

Thanks,
Desperado

8

In reply to dave_59:

I have a similar problem where Questa 10.2c complains about invalid port.

My VHDL type is:
type test_st_t is
record
data_1: std_logic;
data_2: std_logic;
end record;
type test_a_t is array(3 downto 0) of test_st_t;

The generated verilog out of this (from Questa mixedsvvh option):
typedef struct
{
logic data_1;
logic data_2;
} test_st_t;

typedef test_st_t test_a_t [3:0];

My system verilog testbench is:
import istage_if::*;
module istage_tb_v(
);
wire test_a_t test;
istage_top istage_top_vhdl(
.test(test)
);
endmodule

Maybe that’s where the problem is. Anyway the error is:

** Fatal: (vsim-3362) The type of VHDL port ‘test’ is invalid for Verilog connection (1st connection).