Static factory registration

OVM
1

I have a question about the OVM factory mechanism used to register classes for runtime creation by name, for example:

class MyComp extends ovm_component;
typedef ovm_component_registry #(MyComp, “MyComp”) type_id;
endclass

The typedef alone results in static factory registration, i.e the class does not register with the factory if the typedef is removed. If I understand the LRM correctly, a typedef defines a type. How can merely defining a type (or not) result in different runtime behavior? Is this usage of typedef guaranted to work across simulators, i.e is the behavior guaranteed by the language?

Thank you.

2

A typedef of a parametrized class creates a specialization of a generic class. The static components of a generic class do not come into existence until a specialization of that class is defined, either by a typedef or by creating an instance of class variable. One set of static variables is created for each unique specialization of parameters of a class. This behavior is defined in section 8.24 of the IEEE Std 1800-2009 LRM. Once a specialization of a class type is defined, the static variables need to be allocated and the simulator will evaluate their initialization expressions. BTW, for an nonparametric class, static variables are allocated just by definition of the class; no typedef or instantiation of the type is required.

A static variable may have a declaration initialization expression and the factory uses this feature to call a function that registers a new type with the global factory.

The only issue that may be tool dependent is that if you have a package with a class that registers itself with the factory, but that package is never imported, does the package exist? Depending on each tool’s separate compilation flow, there may be different answers to that question.

Dave Rich

3

Thank you for taking the time to reply.

It seems like my confusion about this was caused by thinking in C++ and not in SystemVerilog. The two languages are different in this regard, even in the nonparametric case, for example:

class test;
static int x=1;
endclass

This causes allocation (and init) in SystemVerilog just by definition of the class, as you point out. It then seems natural to have a typedef with license to allocate and initialize, since typedef is a type definition in SystemVerilog.

The same class in C++ goes like this:

class test {
public: static int x;
};

int test::x=1;

This approach is different from SV in that x isn’t allocated and initialized just by definition of the class, but by declaration (of the variable outside the definition), and since typedef does not declare a variable, it can’t instantiate anything in C++. The instantiation is therefore at point of usage, and that breaks automatic registration to a factory since there is no point of usage. Another thing is that typedefs do not define types either in C++, just synonyms for other types.

The typedef registration of the ovm factory is therefore a surprise from a C++ standpoint (for me at least), especially since the proxy generics can take string parameters and therefore enables an elegant lookup by name.

Erling