Ovm test environment setting : hdl module vs interface

OVM
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1

Hi!
I am a new user of ovm (I used to work with vhdl/verilog based verification methodology)
I am trying to develop a verification environment for a design that communicates with an external adc( spi protocol: cs, sclk etc)

Here is my questions:
1-
As I need a model to emulate the behaviour of the adc,
should I design it as a systemverilog module ? or directly as an interface ?

2-
If the adc’s SV model exists, can I use it as is.
(this model contains/checks all of the adc features ( timing verification of the protocol, data in/data out serialization etc)

Thank you.

2

Please consider starting with UVM; OVM is no longer supported.

It’s going to be hard to answer this question without knowing all the details of your design. Normally, all the physical related characteristics related to the actual interface should go in the SV interface. Timing checks and protocol assertions are ideal for an interface. Typically serialization can go in there too, but if you want the test to modify that behavior in the future, you would be better off putting that into a class.

3

In reply to dave_59:

Thank you for your answer.

DUT functions:
Periodically (predefined period of time), the dut acquires the external adc, gets adc_data, re-formats it into a CAN_frame and sends it through Tx output.

What I have to check:
-adc_data = data sent on the can_frame
-periodicity of the emission

For the adc:
If I choose to put timings checks and serialization into an adc_interface,
how can I connect the transactions to that interface ?

here what I did:
I created the following classes:
–adc_transaction : random 12 bits data inside (data coming from the adc)
–adc_sequence #(adc_transaction)
–adc_sequencer #(adc_transaction)

in the adc_driver class, I do the following :
in task run(): wait for a negedge(adc_interface.cs_n) then I launch task drive(); (cs_n negedge triggers the dut request for a new acquisition)
In task drive(): push the extracted data from the current transaction into (adc_interface.data_in)

what do you think ? is what I did ok ?
Do you have any suggestions?

Thank you so much for your help.