I have written the code for virtual sequencer to control subsequences in the lower sequencers in the IVC verification components-IVC1&IVC2 following the ovm userguide guidelines. When I try to simulate the code wth the MVC test top, I am getting the following error:
# ** Error: (vsim-3046) base/ovm_registry.svh(53): Too many arguments to ‘new’. Expected 0, found 2. # Region: /SATAphy_wrapper_top/ovm_component_registry::ovm_component_registry__11 # ** Error: (vsim-3046) base/ovm_registry.svh(53): Too many arguments to ‘new’. Expected 0, found 2. # Region: /SATAphy_wrapper_top/ovm_component_registry::ovm_component_registry__11
I have tried extending the virtual sequencer from ovm_sequencer & ovm_virtual_sequencer. The error comes only when I am including the sequencer in my code. How to write a virtual sequencer properly?
Hope to get a response to this post. Would be very thankful if someone can attatch some example code.
Thank you so much vaibhav. Can anyone suggest a solution to this problem I am encountering now?
While running my code of virtual sequencer, I am getting the first value of my lower sequence twice. I havr tried by disabling the default sequence of lower sequencers using
set_config_int(“.sqr1", “count”, 0);
set_config_int(".sqr2”, “count”, 0);
set_config_int(“virtual_sequencer”, “count”, 1);
Why is it that the same sequence value is accessed twice?
Can you elaborate what you mean by “getting the first value of lower sequence twice”?
Is it that you get the same data item twice in the lower sequence or something else?
Setting count to 0 only shuts down sequences started automatically using the default_sequence string in the sequencer. You should double check if any sequences are getting started manually in the lower sequencer in which case count doesn’t have any effect.
Thanks Vaibhav. I’ve gone through this example, I can see that lower sequencer is registered to a sequence (upper_2_lower_seq) which translate upper sequence (ATM cells) to lower sequence (APB trans). Ideally lower sequencer act as a slave to upper sequencer for driving upper sequencer’s data by using upper_2_lower_seq.
My requirement is that I want to use the lower_sequencer as both master and slave. ie, It should able to work for its own sequences (APB trans) and whenever high level packets (ATM cells) are available, it should act on upper_2_lower_seq.