hai to all,
i have run my code in modelsim.it is totally working.now when i run my simulation on ncverilog 8.1 errors are coming in ovm src code. like
virtual function string get_type_name (); \
|
ncvlog: E,BADQAL (…/src/package/src//macros/ovm_phase_defines.svh,30|19): Lifetime or qualifier(s) ‘virtual’ not allowed before function declaration.
(include file: ../src/package/src//macros/ovm_phase_defines.svh line 30, include file: …/src/package/src//ovm_macros.svh line 45, include file: ../src/package/src//ovm.svh line 23, file: ../src/package/src/ovm_pkg.sv line 26) virtual function string get_type_name (); \ | ncvlog: *E,NULLEI (../src/package/src//macros/ovm_phase_defines.svh,30|47): zero length escaped identifier [2.7.1(IEEE)]. (include file: …/src/package/src//macros/ovm_phase_defines.svh line 30, include file: ../src/package/src//ovm_macros.svh line 45, include file: …/src/package/src//ovm.svh line 23, file: …/src/package/src/ovm_pkg.sv line 26)
return "NAME``_phase"; \
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ncvlog: E,MI*X (…/src/package/src//macros/ovm_phase_defines.svh,31|11): expecting an ‘=’ or ‘<=’ sign in an assignment [9.2(IEEE)].
(include file: ../src/package/src//macros/ovm_phase_defines.svh line 31, include file: …/src/package/src//ovm_macros.svh line 45, include file: ../src/package/src//ovm.svh line 23, file: ../src/package/src/ovm_pkg.sv line 26) return “NAME_phase`"; \ | ncvlog: *E,EXPCPD (../src/package/src//macros/ovm_phase_defines.svh,31|14): expecting a valid compiler directive [16(IEEE)]. (`include file: ../src/package/src//macros/ovm_phase_defines.svh line 31, `include file: ../src/package/src//ovm_macros.svh line 45, `include file: ../src/package/src//ovm.svh line 23, file: ../src/package/src/ovm_pkg.sv line 26) return `"NAME_phase`”; \
i m trying with ovm-1.1 as well as ovm-1.0.1.is ncverilog is not supporting ovm?
Hi.
You didn’t tell us your compile commands, so it’s tricky to pinpoint the problem…
Generally it’s best to use “irun” to compile with OVM, as it takes care of certain things for you such as running the SV pre-processor that’s used by IUS 6.2 and 8.1.
If you must run without irun, here’s an example of how to make it work:
In IUS 6.2
and IUS 8.1, it is necessary to first instrument OVM using svpp. svpp is
a preprocessor which identifies parameterized types and specializations
and instruments the parameterizations and specializations with unique
unparameterized names. To precompile the OVM library using ncvlog, use
the following steps:
Create a cds.lib and hdl.var file (the hdl.var file can be empty) in
the directory where you want to compile the library. #cds.lib
define ovmlib ./ovmlib
Create the local ovmlib directory
Run svpp on the ovm_pkg.sv file. This will put the instrumented code in
the INCA_libs directory.
$ ncroot/tools/urm/bin/svpp -incdir /src /src/ovm_pkg.sv
Run ncvlog on the instrumented files by pointing your incdir path
to the instrumentation area ahead of the OVM area.
$ ncvlog -work ovmlib -incdir INCA_libs/svpplibs/specials
-incdir INCA_libs/svpplibs//src
INCA_libs/svpplibs//src/ovm_pkg.sv
-sv -nowarn PMBDVX
Now, you can use this precompiled library the same way you use any other
ncvlog generated library.
hai sir,
i have done what u said, in this thread.ovm package is compiled.i have some common defines and enums in which ncverilog gives error.error coming is
USB_SET_FTR = `USB_SET_FTR,
ncvlog: *E,SVECLM (…/src/package/nvs_usb_sv_enum_pkg.sv,59|33): The value of an enumeration constant must be defined with a literal (temporary implementation restriction).
did ncverilog didn’t support enums .or i have to compile them first with svpp and how to do it plz tell me?
I agree with Stephen that it is difficult to provide good answers without looking at your code.
I just tried with a simple example to show that nc supports macros in enums. See below:
//define.sv
module top;
`define GOOD 0
`define BAD 1
typedef enum {G = `GOOD, B = `BAD } sometype;
class someclass;
rand sometype e;
endclass // foo
someclass c;
initial begin
c = new;
void'(c.randomize());
$display ("Enum value is %s and it's numeric value is %d", c.e.name(), c.e);
end
endmodule // top
command to run this example is:
% irun define.sv
Here is the output:
nclx38:/home/umer/work/82ibeta> irun define.sv
irun: 08.10-s006: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
Loading snapshot worklib.top:sv .................... Done
ncsim> source /home/umer/downloads/ius/tools/inca/files/ncsimrc
ncsim> run
SVSEED default: 1
Enum value is B and it's numeric value is 1
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
If this is an ncverilog specific issue, I suggest that you file a service request using sourcelink.cadence.com.
I m running my ovm code in ncverilog.first of all ncverilog is only supporting ovm-2.0.in my code there is a file in which all enums are defined .for example
typedef enum bit [7:0] {USB_DATA0={~USB_PID_DATA0,USB_PID_DATA0},
USB_DATA1={~USB_PID_DATA1,USB_PID_DATA1},
USB_DATA2={~USB_PID_DATA2,USB_PID_DATA2},
USB_MDATA={~USB_PID_MDATA,USB_PID_MDATA},
USB_NO_DT={8’d0}
}
data_pid;
file which have all of these defines is also included in enum file.
ncvlog is showing error:
ncvlog: *E,SVECLM (…/src/package/nvs_usb_sv_enum_pkg.sv,117|18): The value of an enumeration constant must be defined with a literal (temporary implementation restriction).
typedef enum bit [7:0] {USB_DATA0={~USB_PID_DATA0,USB_PID_DATA0},
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ncvlog: *E,SVECLM (…/src/package/nvs_usb_sv_enum_pkg.sv,124|35): The value of an enumeration constant must be defined with a literal (temporary implementation restriction).
USB_DATA1={~USB_PID_DATA1,USB_PID_DATA1},
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when i m replacing these defines with there values but still same errors are coming.
what can i do to remove these errors?
<!-- toctype = X-unknown --> <!-- toctype = text --> <!-- text -->
Are you trying to concatenate fixed values in:
USB_DATA0={~USB_PID_DATA0,USB_PID_DATA0}
If so, I think the concatentation is confusing the enumerated type, e.g. maybe try the following (assuming USB_PID_DATA0, etc is fixed at compile time):