Inline constraint vs built-in constraint

OVM
1

Hi, experts,
I am using Questa6.5d and OVM. And my question is:
Will inline constraints overwrite built-in constraints?
for examples,

class trans extends ovm_sequence_item;
   rand logic[31:0] addr;
   ...
   constraint **<font color=red>addr_c1</font>**{...}
endclass

class seq1 extends ovm_sequence #(trans);
   rand logic[31:0] s_addr;
   ...
   task body();
        `ovm_rand_send_with(req, {addr ==  s_addr;})
   endbody
endclass

class vseq extends ovm_sequence;
   ...
   task body();
        `ovm_do_with(s1, {<font color=red>**addr_c2**</font>})
   endbody
endclass

In my testbench, constraint called addr_c2 make addr_c1 not work again! Why is not addr_c1 & addr_c2 and both of them work for randomize!

Thanks in advance.

2

As per me it is not possible to overwrite built in constraint.
You have to make constraint mode off before randomizing else extend your sequence and override constraint by writing constraint with same name.
As `ovm_do_with first creates item then randomize it so whenever it randomizes item it considers both constraints and try to resolve both as constraint solver rules.

3

Agree with akki. Either extend your sequence item and use the factory to select it, or don’t use the ovm_do macro and use s1.addr_c1.constraint_mode(0) statement directly.

Also, you cannot pass a constraint label (addr_c2) as an argument to randomize with{}.

Dave

4

Thanks Dave & akki for ur advice:)
I made a mistake. Both of inline and built-in constraints work.