I have simulation that some of the design reg changed due to force from the validation env.
How can i add my log some tracker that will show me which file/line number did the force?
Is it possible?
Thanks a lot
In reply to kobipinhas:
Consult your tool debug doc, it should be able to support this. Which tool do you use?
Srini
www.verifworks.com
In reply to Srini @ CVCblr.com:
i am using vcs.
i add the flag -force_list <file_name> and it wroked