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  • How to issue ACK sequence on RX sequencer upon getting DATA packet from TX interface?

How to issue ACK sequence on RX sequencer upon getting DATA packet from TX interface?

OVM 2533
reactive sequence 1 passive agent 1 master and slave 1
jjeanjacob
jjeanjacob
Full Access
2 posts
March 18, 2017 at 7:24 am

Hello,

Kindly have a look at the below query.

A. DUT details:

I have a DUT with a TX interface and an RX interface.

Both (TX and RX) are symmetric with only 2 pins - data (4-bit wide) and clock. Two kinds of packets can be issued on either interface - DATA packet or ACK packet. When the DUT through the TX interface issues a DATA packet to the external system, it expects an ACK packet back on the RX interface. Similarly, when the RX interface issues a DATA packet to the DUT, the DUT responds with ACK packet on the TX interface.

The packets look like:
1. DATA packet (nibbles) :IDLE.... | SYNC | ADDR 1-2 | DATA 1-8 | IDLE.... (The packet starts with SYNC nibble, (1+2+8=11 nibble wide))
2. ACK packet (nibbles) : IDLE ... | SYNC | ACK | IDLE .... (2 nibble wide)

B. OVM Testbench details:

I have created a TX agent and an RX agent. The TX agent is passive (only monitor) since it only needs to monitor DATA/ACK packets coming on the TX interface. The RX agent is active and can drive DATA and ACK packets onto the RX interface.

C. My question:

I need to issue an ACK packet on RX interface when I receive a DATA packet on TX interface. However, I am wondering how to get the TX monitor to convey this information to the test. (I am starting RX sequences on the RX sequencer in the run phase of the test). As far as I understand, the monitor is only supposed to talk to analysis components connected to it.
One way I was thinking of getting this done is to add a TX sequencer and TX driver - make the TX agent active. I can then issue a sequence on the TX sequencer causing the TX driver to wait till a DATA packet is received (effectively, monitor the TX interface without driving anything). I can then issue an ACK packet on the RX interface.

But I am not convinced that this is the correct way to solve this.

Searching for similar queries in this forum did return results, but I was not able to map any to this exact scenario.

Could you please suggest a method to go about this?

Thanks in advance

Regards,
Jean

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Solution

Tudor Timi
Tudor Timi
Full Access
333 posts
March 20, 2017 at 2:06 am

In reply to jjeanjacob:

Your RX interface is behaving as both an active master (it drives traffic, i.e. DATA packets) of its own volition, but also as a re-active slave (it drives ACK packages in response to other traffic). While not exactly the situation described there, this paper could be helpful.

What I can imagine in your case is the following:

  • a virtual sequencer that brings both the RX and TX sides together; it's going to have to contain an analysis port connected to the TX monitor, to be able to react to DATA packets sent on that interface
  • on the virtual sequencer you start a sequence (let's call it the reponder sequence) that forever waits for TX DATAs; when one comes you start an ACK on the RX sequencer
  • business as usual on the RX side regarding DATA packets (meaning you start master sequences as before)

It would be possible to do this with only one sequencer, by creating a subclass of your sequencer to add the analysis port stuff and making sure you instantiate this sequencer as your RX sequencer. This is, I think, less clear from a testbench architecture point of view and I'd rather use composition than inheritance whenever possible.

You'll need to take care about any potential issues with parallelism here. For example, what happens if you get a DATA on the TX side and you send a DATA on the RX side before sending an ACK? A sequencer provides you the tools for this, by allowing a sequence to grab/lock it. For example, you can monitor a TX DATA packet and in your responder sequence you can grab the RX sequencer to get your ACK ahead of any DATA packets that might have been already scheduled by your RX master sequence.

Constrained random thoughts on SystemVerilog and e: http://blog.verificationgentleman.com/

jjeanjacob
jjeanjacob
Full Access
2 posts
March 21, 2017 at 2:28 am

Hi Tudor,

Thanks a lot for the detailed reply.

Thanks,
Jean

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