Kindly have a look at the below query.
A. DUT details:
I have a DUT with a TX interface and an RX interface.
Both (TX and RX) are symmetric with only 2 pins - data (4-bit wide) and clock. Two kinds of packets can be issued on either interface - DATA packet or ACK packet. When the DUT through the TX interface issues a DATA packet to the external system, it expects an ACK packet back on the RX interface. Similarly, when the RX interface issues a DATA packet to the DUT, the DUT responds with ACK packet on the TX interface.
The packets look like:
1. DATA packet (nibbles) :IDLE.... | SYNC | ADDR 1-2 | DATA 1-8 | IDLE.... (The packet starts with SYNC nibble, (1+2+8=11 nibble wide))
2. ACK packet (nibbles) : IDLE ... | SYNC | ACK | IDLE .... (2 nibble wide)
B. OVM Testbench details:
I have created a TX agent and an RX agent. The TX agent is passive (only monitor) since it only needs to monitor DATA/ACK packets coming on the TX interface. The RX agent is active and can drive DATA and ACK packets onto the RX interface.
C. My question:
I need to issue an ACK packet on RX interface when I receive a DATA packet on TX interface. However, I am wondering how to get the TX monitor to convey this information to the test. (I am starting RX sequences on the RX sequencer in the run phase of the test). As far as I understand, the monitor is only supposed to talk to analysis components connected to it.
One way I was thinking of getting this done is to add a TX sequencer and TX driver - make the TX agent active. I can then issue a sequence on the TX sequencer causing the TX driver to wait till a DATA packet is received (effectively, monitor the TX interface without driving anything). I can then issue an ACK packet on the RX interface.
But I am not convinced that this is the correct way to solve this.
Searching for similar queries in this forum did return results, but I was not able to map any to this exact scenario.
Could you please suggest a method to go about this?
Thanks in advance