One approach would be to just do data integrity checks using scoreboard and use temporal assertions to check write protocol (and read). If you start using UVM Reg (a la VMM-RAL), then back-door is fairly easy to implement (of-course you can do it outside too). Also since you need to take care of scenarios (assuming you use CRV - Constrained Random Verif):
1. Multiple writes before a single read
2. Reads to unwritten locations
(We show both of the above during our popular SystemVerilog & methodology training classes, see: http://www.cvcblr.com/trainings ).
Also you may need to take care of:
1. Posted writes/reads
2. Coherency (in case of multi-master/multi-slave - you maynot need it in your simple case)
Hope this sheds some light. Good luck. In case you are looking at instructor lead step-by-step training into these topics, feel free to contact us via: http://www.cvcblr.com/trainings