Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Embedded Software Debug Using Integrated Codelink and Visualizer - 12/8
      • Visualizer Coverage - November 19th
      • Events Calendar

    • On Demand Seminars

      • I'm Excited About Formal...My Journey From Skeptic To Believer
      • Interactive Debug Techniques
      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
Ask a Question
OVM
  • Home /
  • Forums /
  • OVM /
  • How analysis port write method handles the write method when there is a packet from multiple interfaces written simultaneously ?

How analysis port write method handles the write method when there is a packet from multiple interfaces written simultaneously ?

OVM 2533
prashanth.billava
prashanth.billava
Full Access
24 posts
September 12, 2016 at 1:38 am

Hi Team,

I am creating the packet out of one interface and sending it over analysis port write method. Example code is shown below.

class collector extends ovm_monitor;
 
  ovm_analysis_port #( trans_item ) trk_port;
 
  `ovm_component_utils_begin(collector)
 
  // Methods 
  extern function new (string name = "collector", ovm_component parent = null);
  extern function void build();
  extern task run();
  extern task collect_trans_1();
  extern task collect_trans_2();
 
endclass: collector
 
//Only relevant code is shown below.
task collector::run();    
    fork
        collect_trans_1();
        collect_trans_2(); 
    join_none
endtask : run
 
task collector::collect_trans_1()
  trans_item trans_item_1;
  trans_item_1.data = interface1.data;
  trans_item_1.address = interface1.address;
  trk_port.write(trans_item_1);
endtask: collect_trans_1 
 
task collector::collect_trans_2()
  trans_item trans_item_2;
  trans_item_2.data = interface2.data;
  trans_item_2.address = interface2.address;
  trk_port.write(trans_item_2);
endtask: collect_trans_2

Even though both the interfaces are different, I am creating the packet of same type (trans_item) out of it and sending it over analysis_port. This is working fine so far.

Now my question is, If I receive the transaction simultaneously on the bother the interfaces (interface1 and interface2), will
my analysis port (trk_port) be able to handle it?

Could someone kindly explain.

Thanks in advance

Replies

Log In to Reply

Solution

Solution

dave_59
dave_59
Forum Moderator
8273 posts
September 12, 2016 at 5:07 pm

In reply to prashanth.billava:
The code that you show does not construct a trans_item or what the write() method does that is on the other side of the analysis port. So there is no way to know what problems there may be.

- Dave Rich

kddholak
kddholak
Full Access
94 posts
September 12, 2016 at 5:48 pm

In above code , class collector has one analysis port so collector should have one write method. On the one write method, sends trans_item1 and trans_item2. How are the port connected other end ?

prashanth.billava
prashanth.billava
Full Access
24 posts
September 15, 2016 at 3:47 am

In reply to dave_59:

Hi Dave,

I have missed to add the construction part. Thanks for pointing it out (Assume that it is there)

And top level code looks like this: (ignore if there is any typo)

class soc_env extends ovm_component;
 
    // Instantiate collector and tracker
    collector                   m_collector;
    tracker                     m_tracker;
 
    // Factory registration
    `ovm_component_utils(soc_env)
 
    // Methods 
    extern function         new(string name = "soc_env", ovm_component parent = null);
    extern function void    build();
    extern function void    connect();
    extern task run(); 
 
endclass : soc_env
 
//Only relevant methods are shown
function void soc_env::connect();
    super.connect();
    // collector analysis port connected to tracker analysis export  
    m_collector.trk_port.connect(m_tracker.txn_port_imp.analysis_export);
endfunction
 
// Tracker component looks like this. 
 
class tracker extends ovm_monitor;
 
    // Factory registration
    `ovm_component_utils(tracker)
 
    // Ports  
    tlm_analysis_fifo #( trans_item )  txn_port_imp;
 
    // Methods
    extern function new(string name = "tracker", ovm_component parent = null);
    extern function void build();
    extern task run(); 
    extern task track_txn();
 
endclass : tracker
 
task tracker::run();
    super.run();
    fork
      track_txn();
    join_none  
endtask // run
 
task tracker::track_txn();
    trans_item transaction_item;  
    forever begin
        txn_port_imp.get(transaction_item); 
        // I will work on this item here to print in table format
 
    end
endtask

In tracker I am just getting the item and just displaying in the tracker format.
Now my query is, if i receive the transactions simultaneously on both the interface (interface1 and interface2) at collector side, do I face any issues while getting the item at tracker side?

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock