How to access a VHDL internal signal in a system verilog module as we do for verilog (e.g. top.mod_i.signal_name). I tried using the same thing but it doesn’t work.
I have a VHDL component with a signal ‘sig’ declared in its architecture and it is not a port. This VHDL component is instantiated in a system verilog top module. Now, I want to access VHDL signal ‘sig’ from top.sv.
Is there any way to do this?
Thanks and regards,
If you are using Questa, the simplest solution is to use the Signal Spy feature to alias a Verilog variable to an embedded VHDL signal
You can also create a SV module with a type-compatible input port and use the SystemVerilog bind statement to remotely instantiate it underneath the VHDL object and connect the VHDL signal to the input port. You can then access the Verilog port from within that module (e.g. for use in assertions).
-Kurt
VHDL does not allow hierarchical references, unlike Verilog.
I guess most simulators interpret that to also mean that Verilog hierarchical references cannot end in a VHDL block.
In NCSim you can use the nc_mirror utility to clone a signal’s value from any point in the hierarchy into anywhere else. This is probably analogous to Questa’s Signal Spy, though I have not seen that myself.
I tried system verilog “bind” and I am able to proble the embedded signals in vhdl entity.
Thank you
-vikas
The module which I am binding to VHDL signal is instantiated inside the VHDL module. So, I can write the assertions for the binded signal. It serves the purpose of writing assertions on any internal signals.
My requirement is to send the embedded vhdl signal to scoreboard but the binded module instantiates inside the VHDL object and the vhdl signal can not be access from top.
So, the bind is not serving my purpose. Is there any way of doing this which is simulator independent?
The only way I know that is simulator-independent and that has already been explained here is to declare signals you want to play with in a global package.
Else, you can use some `ifdef to switch between nc_mirror and signal_spy features.