Before start asking question, here is a little background of my work.
I'm doing memory testing using recommended way in OVM.
For read request and read data cycle is happen one clock cycle difference. For example, at first clock cycle, agent initiates a read request to the memory, the read data returning from memory at second clock cycle, then the monitor gets the transaction on the interface at second clock cycle and do analysis_port.write(), follow by scoreboard gets the data on second clock cycle.
The read data cycle is possible to happen at the same time as write cycle, read cycle and idle cycle (happen on the same clock cycle), in this case, i use fork join method for write cycle function, read cycle function, read data cycle function and idle cycle function. Each function has its own analysis_port.write(). For example,
The question is, by doing this, since all four functions are running in parallel, would the simulator executing the second function call before finish executing the first function call?
I try to remove the fork join to make it sequential function call, however I see my data that sent through analysis port get overwritten by second function call and getting unexpected result in scoreboard.
May I know how usually people code the monitor for memory DUT to handle read cycle and read data cycle? Since it can be overlapped.