Design Register Model on OVM

OVM
,
1

Hi all,

i am designing VIP.in that i don’t have any RTL or any MEMORY MODULE.

i am designing memory model just by checking address

like, this

class MEMORY();
virtual interface AHB;

if(HADDR == 'h0010)
reg1 = HWDATA;
if(HADDR == 'h0012)
reg1 = HWDATA;
.
.
.
.
.

endclass

this way m going to design my Memory model.

is it possible to write RAL model without DUT or MEMORY BANK? I have confusion that without RTL how can i use RAL model, Hoe can i use back door access, in which i have to use HDL path of the register. Please help me,!!!

I have created RAL for spi, but that time i had SPI RTL.

please reply ASAP…!!

2

The Register Abstraction Layer can be used to model any memory/register map you desire, whether it exists in RTL or not. If there is no RTL mapping for the register definitions, then don’t define a back door path. The back door path is an optional component of a register map.

3

In reply to cgales:

class memory_bank extends ovm_component;
`ovm_component_utils (memory_bank)

virtual interface AHB;

reg [31:0] ADV_TX_TYPE;
reg [47:0] SRC_ADDR;
reg [47:0] TGT_ADDR;


function new (string name="memory_bank", ovm_component parent);
	super.new (name,parent);
endfunction : new

function void build();
	mem_data = new ("mem_data",this);
endfunction : build

extern task run();

endclass : memory_bank

task memory_bank::run();
forever
begin
@(posedge clk);
if (AHB.rst)
begin
ADV_TX_TYPE = 'd0;
SRC_ADDR = 'd0;
TGT_ADDR = 'd0;

	end

	else if (AHB.Hwrite)
	begin
		case (AHB.WADDR)
			'h10 : ADV_TX_TYPE		 = AHB.data;
			'h11 : SRC_ADDR[31:0]		 = AHB.data;
			'h12 : SRC_ADDR[47:32]		 = AHB.data;
			'h13 : TGT_ADDR[31:0]		 = AHB.data;
			'h14 : TGT_ADDR[47:32]		 = AHB.data;
			
		endcase

		
	end

	
end

endtask : run

it may be syntax error in above code , ignore it

this is the way m going to design Memory. is it possible to write RAL model for this Memory model.

if yes than please explain me the flow. how write, read …API will work? the exact flow.
pleass help me. thanks.