Default Sequence for a Sequencer?

OVM
1

Hi All,

I have been using sequences in my environment.

In my environment, there are multiple drivers (called as masters) each with a sequencer.

As per xbus example in the OVM examples library, I have been applying default sequences to some of the masters through “set_config_string” on “default_sequence” string.:)

What happens if am NOT assigning any sequence as “default sequence” to a driver? Which sequence from my sequence library will be used?:confused:

Lets’ say I have only three sequences in my sequence library & there are ten masters(drviers) in my env each with a sequencer.
How does the default sequence mechanism works here?

Is it possible to assign same sequence to more than one driver?:confused:

How can I add sequence to “ovm_simple_sequence”?

Please provide me explanation with some examples.

Thanks in advance.:D

TVAR

2

Hello,
please find here below some comments, I hope these will help.

As per xbus example in the OVM examples library, I have been applying default sequences to some of the masters >through “set_config_string” on “default_sequence” string.

I would say in a different way, using “default_sequence” you are assign the default sequence to be
used by the sequencer (not on the driver), with a sequence defined in the sequence library.
The driver will consume them, applying the data items from the transaction to the interface.

What happens if am NOT assigning any sequence as “default sequence” to a driver?
Which sequence from my sequence library will be used?

The default value for default_sequence is ovm_random_sequence.
On sequencer there are three built-in sequences: ovm_random_sequence, ovm_exhaustive_sequence, and
ovm_simple_sequence.
User-defined sequences (the ones coming from sequence library) are loaded into the sequencer’s sequence
queue prior to the run simulation phase. Upon entering the run phase, the sequencer starts
the default_sequence and the transactions start flowing.
You can configure the default sequence to be any user-defined sequence or built-in sequence.

Lets’ say I have only three sequences in my sequence library & there are ten masters(drviers)
in my env each with a sequencer. How does the default sequence mechanism works here?
See above for default sequence.

If you have some masters and you like to assign a specific sequence to a specific master, use the
set_config_string on your test. Please take a look on xbus/examples/test_lib.sv, the example show how
to set the default sequence to xbus_demo_sve0.xbus0.masters[0].sequencer with “read_modify_write_seq”
from the master sequence library.

Is it possible to assign same sequence to more than one driver?

See above, you will not assign the sequence to the driver, but to the sequencer.

How can I add sequence to “ovm_simple_sequence”?

This sequence is a built-in sequence which is pre-loaded into the sequencer;
it calls the `ovm_do(item), where item is a property on omv_sequence.
You can use the set_config_string to use the simple sequence a default sequence.

Thanks in advance.

You are very welcomed, I hope this will help,
Riccardo

3

Hi Riccardo,

Thanks for the reply.:D

I have used driver in place of sequencer inadvertently, as my env has one sequencer in each of the driver(master).:)

I am trying to get a clear picture on sequencers.

Please find my queries on your reply.

The default value for default_sequence is ovm_random_sequence.
On sequencer there are three built-in sequences: ovm_random_sequence, ovm_exhaustive_sequence, and
ovm_simple_sequence.
User-defined sequences (the ones coming from sequence library) are loaded into the sequencer’s sequence
queue prior to the run simulation phase. Upon entering the run phase, the sequencer starts
the default_sequence and the transactions start flowing.
You can configure the default sequence to be any user-defined sequence or built-in sequence.

Say I have ten sequencers in my env, each coupled with a driver. I have assigned default_sequence to six of those sequencers.

What happens to the rest four sequencers?

Whether they will pickup sequences from ovm_random_sequence? If so in which manner, like one after another or randomly?

Other way what will be a default_sequence for a sequencer, if user defined is NOT assigned?

If you have some masters and you like to assign a specific sequence to a specific master, use the
set_config_string on your test. Please take a look on xbus/examples/test_lib.sv, the example show how
to set the default sequence to xbus_demo_sve0.xbus0.masters[0].sequencer with “read_modify_write_seq”
from the master sequence library.

Using set_config_string, can I assign same sequence to two or more sequencer (like “read_modify_write_seq” → masters[0].sequencer & masters[1].sequencer at a time)? If so both the sequence items will be applied in parallel or sequential manner to the interface?

Thanks in advance

TVAR

4

Hello Again,
here below my comments:

Say I have ten sequencers in my env, each coupled with a driver.
I have assigned default_sequence to six of those sequencers.
What happens to the rest four sequencers?

The unassigned will use ovm_random_sequence

Whether they will pickup sequences from ovm_random_sequence?

Yes. Precisely: this sequence randomly selects and executes sequences
from the sequencer’s library (excluding ovm_random_sequence and ovm_exhaustive_sequence).
The number of sequences executed depends on the count field of the sequencer.
If count is set to -1, the random sequence will randomize a number between 0 and
ovm_sequencer::max_random_count. If count field not -1, then count sequences
will be executed by ovm_random_sequence.

To better understand please check the test_lib.sv on the xbus example, you should find the ovm_print_topology command at line 49.
Comment the line above (depth, line 48) to get the whole print-outYou should see the above mentioned count, default_sequence, etc.

For sequencer config understanding, regardless the verification results,
edit the file xbus_demo_sve.sv and modify the num_masters and slave_masters to 2.
then run again and check the topology on log file, you will see master/slave[0] with
the default_sequence set with the ones by set_config_string on test, the [1] will
be with ovm_random_sequence.

If so both the sequence items will be applied in parallel or sequential manner to the interface?

I guess your meaning here is more “how I can control and apply at the right time the needed sequences ?”
You should take a look into virtual sequence and virtual sequencer.

Regards,
Riccardo

5

Yes. Precisely: this sequence randomly selects and executes sequences
from the sequencer’s library (excluding ovm_random_sequence and ovm_exhaustive_sequence).
The number of sequnces executed depends on the count field of the sequencer.
If count is set to -1, the random sequence will randomize a number between 0 and
ovm_sequencer::max_random_count. If count field not -1, then count sequences
will be executed by ovm_random_sequence.

Hi Riccardo,

Note that included in the set of sequences that ovm_random_sequence chooses, is the ovm_simple_sequence. This sequence requires that you have a factory type override on the sequencer, so that it will generate one of your transaction types. (Otherwise, you will get a runtime factory error when this sequence tries to execute.) This is the purpose of the `ovm_update_sequence_lib_and_item(your_type) macro.

I almost never want this sequence to be chosen, and I wish that ovm_random_sequence would not include it. Is there a way to disable this sequence?

Thanks,
-Kurt

6

Hello Kurt -

As Ric points out ovm_simple_sequence is a basic sequence that randomizes one item. It is useful more during early phases of development of a UVC to randomize all aspects of transactions and do basic debug.

We envision that most users will create their own sequences and use default_sequence parameter in the sequencer to set it appropriately.

If you want to remove ovm_simple_sequence from random selection there are a number of ways for doing this.

One way is to write your own sequence to exclude simple as follows:

class infinity_minus_sequence extends ovm_sequence;
// Constructor and OVM automation macros here

  function new(string name="infinity_minus_sequence");
    super.new(name);
  endfunction

  `ovm_sequence_utils(infinity_minus_sequence, xbus_master_sequencer)    

  virtual task body();
   // Run any sequence in the sequence library except a_seq.
   for (int i=0; i < p_sequencer.count; i++)
     begin
       assert( this.randomize(seq_kind) with { 
         seq_kind != get_seq_kind("ovm_simple_sequence"); } );
        // Invoke a sequence of the selected kind.
        do_sequence_kind(seq_kind);
     end
  endtask : body
endclass

And then you can invoke this sequence as you default sequence on a specific sequencer from a test as:

class infinity_minus extends xbus_demo_base_test;

  `ovm_component_utils(infinity_minus)

  function new(string name = "infinity_minus", ovm_component parent=null);
    super.new(name,parent);
  endfunction : new

  virtual function void build();
    // Set the default sequence for the master and slave
    set_config_string("xbus_demo_sve0.xbus0.masters[0].sequencer",
      "default_sequence", "infinity_minus_sequence");
    set_config_int("xbus_demo_sve0.xbus0.masters[0].sequencer",
      "count", 20);
    set_config_string("xbus_demo_sve0.xbus0.slaves[0].sequencer", 
      "default_sequence", "slave_memory_seq");
    // Create the sve
    super.build();
  endfunction : build
endclass

I ran this code with the xbus example and it ran correctly for me.

Another way is to type/instance override ovm_simple_sequence to do nothing.

Let us know if this satisfies your requirements.

Regards,

Umer

7

To better understand please check the test_lib.sv on the xbus example, you should find the ovm_print_topology command at line 49.
Comment the line above (depth, line 48) to get the whole print-outYou should see the above mentioned count, default_sequence, etc.
For sequencer config understanding, regardless the verification results,
edit the file xbus_demo_sve.sv and modify the num_masters and slave_masters to 2.
then run again and check the topology on log file, you will see master/slave[0] with
the default_sequence set with the ones by set_config_string on test, the [1] will
be with ovm_random_sequence.

Hi Riccardo,

In my environment, I haven’t used printer.knobs.depth assignment.

I have an array of 12 sequencers with only one sequence library.

I am getting the print out display about default sequence assigned for each sequencer (0 to 11) along with test bench topology.

But am getting display for all sequencers (for those whose count value has been set ‘0’).

It there a way to switch off printer display for a specific sequencer?

thanks in advance.

TVAR