Basically the objective is to reduce the number of lines for initiate a transaction from APB master BFM to my design. By doing this I can just write something like this to initiate a transaction, instead of writing 4 lines of code
*mem_wr('h04, 'hFFFF0000;*
I understand that to use the start_item() and finish_item(), it must be done within ovm_object or ovm_sequence_item. May I know how to code this thing out and how to use it in my test sequence and where should I import/include this class?
Excellent objective, Eric. There is not much to it–in fact you have most of the “guts” to what the task would look like. Start_item and finish_item are methods of the uvm_sequence #() class, so you must call them via a sequence handle or from within a uvm_sequence extension.
One solution would be to write a base sequence class that contains the mem_wr and any other convenience methods, then have your test sequences extend from that base class:
To give you one more alternative, you could instead encapsulate the write task in a static method of a utilities class. This lets you write test sequences that do not have to inherit from a base sequence class.
class my_bus_utils;
static task mem_wr(addr_t addr, data_t data, uvm_sequence_base seq);
...same as above except use seq handle to start/finish:
seq.start_item(write_item);
seq.finish_item(write_item);
endtask
endclass
The test sequence would then use the above utility class as follows:
I’m pretty new in the OVM and system verilog, so I might be asking simple questions.
My verification environment is having a base_test (extends from ovm_test) and it does the BFM configuration work. In my test sequence, it has two classes, which are
I tried to `include the mem_cyc.svh in the base_test, compile error with this message ** Error: tests/testing.svh(78): (vlog-7027) Dotted name (‘mem_wr’) not found in current scope. Note that hierarchical references are not allowed from within a package or $unit.
I tried to `include it in the test sequence (testing.svh), same error pops up.
May I know what is wrong with the coding?
I’m thinking that can I have the task() embedded in my base_test? How should I do that?
Now, if you define the mem_wr task in a base sequence, your test sequence must extend from that base sequence if it is to “see” the mem_wr task. Your test sequence extends mstr_sequence, not mem_cyc, hence the compiler error.
class testing_seq extends mem_cyc; // <<---- extends mem_cyc
function new (....)
virtual task body;
...
mem_wr('hAB, 'hBEEF);
endtask
endclass