Constraining Random Variables inside a function!

OVM
1

Hello,

I have rand variables of this form in my ovm_sequence.

class dly_config_seq extends quad_rgm_sequence;
 
  dly_0_c dly_0; 
  bit  dly_0_reg_cs;

  dly_1_c dly_1; 
  rand bit  dly_1_reg_cs;

  dly_2_c dly_2; 
  rand bit  dly_2_reg_cs;  

  dly_3_c dly_3; 
  rand bit  dly_3_reg_cs;  

  ovm_rgm_register_base base_reg;
 
  `ovm_object_utils(dly_config_seq )

  function new(string name="dly_config_seq ");
    super.new(name);
  endfunction

  function void calculate_quad_dly(condition);
      if(condition)
  	constraint dly_3_reg_cs inside [3:5];
     else 
  	constraint dly_3_reg_cs inside [1:5];
  endfunction
endclass

But I get a syntax error - Illegal use of constraint. Can’t I constrain a variable inside a function based on certain conditions?

Thank you in advance for helping.

2

This is really a SV language question.

The correct constraint syntax should be in the main body of your sequence class:

class dly_config_seq extends quad_rgm_sequence;

dly_0_c dly_0;
bit dly_0_reg_cs;

dly_1_c dly_1;
rand bit dly_1_reg_cs;

dly_2_c dly_2;
rand bit dly_2_reg_cs;

dly_3_c dly_3;
rand bit dly_3_reg_cs;

bit condition; // This also need to be added

ovm_rgm_register_base base_reg;

`ovm_object_utils(dly_config_seq )

function new(string name="dly_config_seq ");
super.new(name);
endfunction

// Constraint within body of your sequence:
constraint dly_3 {
if(condition)
dly_3_reg_cs inside [3:5];
else
dly_3_reg_cs inside [1:5];
}

endclass
3

Hi Pratyaksha,
You might want to look at “inline randomization” feature in SV. You could then use

function void calculate_quad_dly(condition);
      if(condition)
  	xactn.randomize with {dly_3_reg_cs inside [3:5];}
     else 
  	xactn.randomize with {dly_3_reg_cs inside [1:5];}
  endfunction

You would need to move this function to a wrapper class though.

As an extended note, SV 2012 standard is adding “soft constraints too”. Soon you may expect support for this in EDA tools. See: SystemVerilog for Verification: Introducing soft constraints in SystemVerilog 2012 for a quick introduction to this new feature.

HTH
Ajeetha, CVC