Connect driver to ported interface modport

OVM
1

i am having a problem with interfaces that are port based.

interface _if (input clk, rst, inout signal);

modport master (input clk, rst, output signal);

When I use driver code:

protected virtual interface _if.master m_if;
   ...
task run()
    m_if.signal = trans.signal;    or    m_if.signal <= trans.signal;
endtask;

Then Questa complains with the following error:

Error: (vsim-3044) … Usage of ‘m_if.signal’ inconsistent with ‘net’ object.

What do I need to do to make this work?

2

You cannot make procedural assignments to wires - interface or no interface.

See my DVCon12 paper “The missing Link: The Testbench to DUT connection” for some suggestions.

3

In reply to dave_59:

Yes, inside the interface, declare that signal as logic.

4

The main issue is that I wanted to connect the driver to the DUT using the bind construct, connecting the generic port names of the driver to the specific names of the DUT. This is easiest with ports.
Is there a similar construct which offers as convenient a method to encapsulate the interface connection as the binding of ports to DUT signals?
The paper cited talks about adding overhead with abstract interface construct and probe functions and is not as convenient.
Is there something better for this particular connection? I can use

assign m_if.signal = dut.signal;

connections in the top, but it does not seem as clean as the bind.
Another possibility is to create modules which has the ports that connect to the DUT and instantiates the interface and connects the interface to the ports.

5

In reply to Larry:

Larry,

You can still use your virtual interface. The suggestion in the paper shows how you can use a continuous assignment or clocking block inside the interface to effectively make procedural assignments to wires

interface _if (input clk, rst, inout signal);

logic signal_driver = 'z;

assign signal = signal_driver;

modport master (input clk,rst,signal, output signal_driver);
endinterface

Then inside your driver, you can do

//as output
m_if.signal_driver <= trans.signal;
// as input
m_if.signal_driver = `z;
trans.signal = m_if.signal;

;

6

This would work for this case. Now, what do I do for the case:

interface _if (input clk, rst, inout signal, inout reply);

modport master (input clk, rst, output signal, input reply);

modport slave (input clk, rst, input signal, output reply);

Is there a way to set it so that the assign drives ‘signal’ for the master and ‘reply’ for the slave.

7

In reply to Larry:

What about two assigns?

interface _if (input clk, rst, inout signal, inout reply);
  logic signal_driver = 'z;
  logic reply_driver = 'z;
  assign signal = signal_driver;
  assign reply = reply_driver; 
  modport master (input clk,rst,reply, output signal_driver);
  modport slave (input clk,rst,signal, output reply_driver);
endinterface
8

Hi Team,
Is it a valid thing to drive the modport signal(which is declared as input)?.
The snippet is as follows.

interface intf();
  logic [7:0]addr;
  logic [7:0]data;
  logic [7:0]r;
modport dut(input addr,data,output r);
modport tb(output addr, data);
endinterface

module top();
intf intf1();
virtual intf vintf=intf1;//virtual interface.
initial begin 
  vintf.dut.addr=8'd8;
  /*vintf.dut.addr=8'd8;
  #10 
  vintf.dut.addr=8'd10;*/
end 
endmodule

One simulator is complaining the compile time error since the signal is declared as i/p in modport.
Other simulator(From different vendor) is not complaining any error !!(passed.

Please let us know if there are any comments on this issue.

Thanks,
Bhaskar