Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • VA Live - Multiple Dates & Locations
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Academy News
      • Contact Us
    • Training

      • Learning @OneGlance (PDF)
      • SystemVerilog & UVM Classes
      • Siemens EDA Classes
Ask a Question
OVM
  • Home
  • Forums
  • OVM
  • Connect driver to ported interface modport

Connect driver to ported interface modport

OVM 2521
Larry
Larry
Forum Access
3 posts
September 05, 2012 at 6:26 pm

i am having a problem with interfaces that are port based.

interface _if (input clk, rst, inout signal);

modport master (input clk, rst, output signal);

When I use driver code:

protected virtual interface _if.master m_if;
...
task run()
m_if.signal = trans.signal; or m_if.signal <= trans.signal;
endtask;

Then Questa complains with the following error:

Error: (vsim-3044) ... Usage of 'm_if.signal' inconsistent with 'net' object.

What do I need to do to make this work?

Replies

Log In to Reply
dave_59
dave_59
Forum Moderator
10898 posts
September 05, 2012 at 8:20 pm

You cannot make procedural assignments to wires - interface or no interface.

See my DVCon12 paper "The missing Link: The Testbench to DUT connection" for some suggestions.

— Dave Rich, Verification Architect, Siemens EDA

mpattaje
mpattaje
Forum Access
36 posts
September 06, 2012 at 6:36 am

In reply to dave_59:

Yes, inside the interface, declare that signal as logic.

Larry
Larry
Forum Access
3 posts
September 06, 2012 at 7:38 am

The main issue is that I wanted to connect the driver to the DUT using the bind construct, connecting the generic port names of the driver to the specific names of the DUT. This is easiest with ports.
Is there a similar construct which offers as convenient a method to encapsulate the interface connection as the binding of ports to DUT signals?
The paper cited talks about adding overhead with abstract interface construct and probe functions and is not as convenient.
Is there something better for this particular connection? I can use

assign m_if.signal = dut.signal;

connections in the top, but it does not seem as clean as the bind.
Another possibility is to create modules which has the ports that connect to the DUT and instantiates the interface and connects the interface to the ports.

dave_59
dave_59
Forum Moderator
10898 posts
September 06, 2012 at 7:59 am

In reply to Larry:

Larry,

You can still use your virtual interface. The suggestion in the paper shows how you can use a continuous assignment or clocking block inside the interface to effectively make procedural assignments to wires

interface _if (input clk, rst, inout signal);

logic signal_driver = 'z;

assign signal = signal_driver;

modport master (input clk,rst,signal, output signal_driver);
endinterface

Then inside your driver, you can do

//as output
m_if.signal_driver <= trans.signal;
// as input
m_if.signal_driver = `z;
trans.signal = m_if.signal;

;

— Dave Rich, Verification Architect, Siemens EDA

Larry
Larry
Forum Access
3 posts
September 06, 2012 at 8:18 am

This would work for this case. Now, what do I do for the case:

interface _if (input clk, rst, inout signal, inout reply);

modport master (input clk, rst, output signal, input reply);

modport slave (input clk, rst, input signal, output reply);

Is there a way to set it so that the assign drives 'signal' for the master and 'reply' for the slave.

dave_59
dave_59
Forum Moderator
10898 posts
September 06, 2012 at 9:26 am

In reply to Larry:

What about two assigns?

interface _if (input clk, rst, inout signal, inout reply);
  logic signal_driver = 'z;
  logic reply_driver = 'z;
  assign signal = signal_driver;
  assign reply = reply_driver; 
  modport master (input clk,rst,reply, output signal_driver);
  modport slave (input clk,rst,signal, output reply_driver);
endinterface

— Dave Rich, Verification Architect, Siemens EDA

Bhaskar chary
Bhaskar chary
Forum Access
4 posts
August 21, 2016 at 2:50 am

Hi Team,
Is it a valid thing to drive the modport signal(which is declared as input)?.
The snippet is as follows.

interface intf();
  logic [7:0]addr;
  logic [7:0]data;
  logic [7:0]r;
modport dut(input addr,data,output r);
modport tb(output addr, data);
endinterface
 
module top();
intf intf1();
virtual intf vintf=intf1;//virtual interface.
initial begin 
  vintf.dut.addr=8'd8;
  /*vintf.dut.addr=8'd8;
  #10 
  vintf.dut.addr=8'd10;*/
end 
endmodule

One simulator is complaining the compile time error since the signal is declared as i/p in modport.
Other simulator(From different vendor) is not complaining any error !!(passed.

Please let us know if there are any comments on this issue.

Thanks,
Bhaskar

Siemens Digital Industries Software

Siemens Digital Industries Software

#TodayMeetsTomorrow

Portfolio

  • Cloud
  • Mendix
  • Electronic Design Automation
  • MindSphere
  • Design, Manufacturing and PLM Software
  • View all Portfolio

Explore

  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Customer Stories
  • Partners
  • Trust Center

Contact

  • VA - Contact Us
  • PLM - Contact Us
  • EDA - Contact Us
  • Worldwide Offices
  • Support Center
  • Give us Feedback
© Siemens 2023
Terms of Use Privacy Statement Cookie Statement DMCA