FWIW, some simulators support sparse arrays even inside design/Verilog code via pragma. IIRC Riviera (Aldec) and VCS supports it.
reg /*sparse*/ [31:0] sparsemem [0:1_048_575];
But with SV around, assoc-arrays are a good choice as it becomes sort of tool independent. But you still may require this trick with old, legacy code. Not sure if NC supports it though.