Any support for Sparse memory from Cadence

OVM
1

Hi all,

I need to implement quite a large amount of memory (4 GB ) in my OVC.

For which Sparse memory modelling will be most efficient one.

I am currently using Cadence IUS2.0 and need to know if cadence supports sparse memory modelling.

Thanks in advance.

Regards
Abhishek

2

Hello Abhishek,

You are correct, you should model memory using a hash. SystemVerilog has associative array that does exactly that.

For example,

logic [31:0] mem[int];

function void add(int address, logic [31:0] data);
mem[address] = data;
endfunction

function logic [31:0] fetch(int address);
if mem.exists(address) fetch = mem[address];
else fetch = 32’hXXXXXXXX;
endfunction

Umer

3

Hi Abhishek,
You can use associative arrays, which are a part of the SystemVerilog IEEE 1800 standard. Associative arrays do not allocate storage until they are implemented and implement a lookup table for the elements of their declared type, so they are ideal for implemening non-contiguous elements of storage.

You can find more information about the implemention of associative arrays along with examples in the SystemVerilog Reference document in cdnshelp (or the direct location to the document is under ncroot/doc/sysverilog/ )

Regards,
Bob

4

Thanks a lot . . . .

5

FWIW, some simulators support sparse arrays even inside design/Verilog code via pragma. IIRC Riviera (Aldec) and VCS supports it.

reg /*sparse*/ [31:0] sparsemem [0:1_048_575];

But with SV around, assoc-arrays are a good choice as it becomes sort of tool independent. But you still may require this trick with old, legacy code. Not sure if NC supports it though.

Ajeetha, CVC
www.cvcblr.com/blog

6

In reply to umery:

Hi Umer,
While Modelling the Memory if there is a requirement of:

  1. Read/Write Locations. (This works for the example stated above)
  2. Read only Locations.
  3. Reserved Locations.
    Then how can we go ahead with associative arrays.

Or any other way to model the same in SV.

Regards,
Ravi