In reply to cooltoad:
There are no truly global functions in SystemVerilog. You can put them in a package and reference them explicitly or import them.
I would advise against adding the function to the top_env class. That means each component that wants to use it has to have a handle to the env, and that creates an undesirable circular dependency.
You could also put your function in a class that you pass to your components via the uvm_config_db.
Your best choice may depend on what other things the function needs access to.