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  • 1 answer
    6,174 views

    Difference Between Associative and Dynamic Array

    Hi All,

    Can any body tell me the

    Difference between Associative and Dynamic Array.

    Regards

    Kunal Mishra

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    Last Activity 1 week 2 days ago by Dinesh Rajendiran
  • 1 answer
    3,938 views

    Constraint X/Z state value error

    Hi all.
    I'm trying to call the macro `ovm_do_on_with upon some predefined sequence.
    The values in the constraint block are legitimate, but still, the simulator says that:
    "State variable 'jtag_seq.Packet.Expected_Data' contains an X/Z value"
    The call is:
    `ovm_do_on_with(jtag_seq , p_sequencer.jtag_sqcr,
    { jtag_seq.Packet.Expected_Data == 0; })

    (using just `ovm_do_on succeeding)
    Thanks,
    Assaf

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    Last Activity 1 week 2 days ago by mseyunni
  • 0 answers
    38 views

    Raise Objections for interrupts

    I wanted to create a Monitor.Monitor will take all the interrupts from RTL .Say there are 5 interrupts INT1,INT2,INT3,INT4,INT5
    When INT1 is Raised.I should raise Objection. It should display "INT1 Objection Raised"
    When INT1 is dropped I shouidl drop objection. dispaly "INT1 Objection Dropped"

    At the end of testcase , Say if INT2 is not dropped it should display
    INT2 Objection didnot dropped.

    I am using like this

    class monitor extends ovm_monior

    task run();
    fork
    forever @(posedge INT1) ovm_test_done.raise_objection(this);

    forever @(negedge INT1) ovm_test_done.drop_objection(this);

    .....INT2..INT5
    join_none
    endtask
    endclass

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    2 weeks 1 hour ago - No activity yet
  • 0 answers
    22 views

    how to set the default value of all elements of a queue to zero before we know the length of the queue?

    Hi,
    Is there way to set all the elements that will be accessed in a queue to a default value of say zero? so that when I use the queue I can go ahead and set some bits to 1 later?

    Thanks in advance

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    Last Activity 2 weeks 2 days ago by dave_59
  • 3 answers
    4,891 views

    Do help pls…prob with assigning interface

    The fatal error I am receiving while trying to simulate my compiled code is:
    The interface port 'HDD_if' must be passed an actual interface.
    I have included the coding i have done in posts below.
    I have tried the code without using clocking blocks also. Still was encountering the same problem. I am using Questa 6.5c and my DUV is in VHDL. I am new to OVM and verification. I am doing this as part of my 1year PG project. Hope I would receive some help in here. Thanking u in advance.

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    Last Activity 3 weeks 1 day ago by devbilaye
  • 3 answers
    5,560 views

    set_global_timeout() doesn't obey time units

    Hi there,

    I've just tried to use set_global_timeout() in my testbench and noticed some strange behaviour. I was hoping someone could point out the gotcha that I'm missing.

    I assumed that in order to set a watchdog timeout value of 1us, I would need to add the following line to my build() function:
    set_global_timeout(1us);

    However, this doesn't have the desired effect. Instead the time units don't seem to be being obeyed and are out by a factor of 1000.

    set_global_timeout(1s) results in a timeout after 1ms.
    set_global_timeout(1ms) results in a timeout after 1us. set_global_timeout(1us) results in a timeout after 1ns.
    set_global_timeout(1ns) results in a timeout after 1ps.
    set_global_timeout(1000) results in a timeout after 1ns.
    set_global_timeout(1000000) results in a timeout after 1us.

    Thanks, Shareef.

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    Last Activity 1 month 5 days ago by dave_59
  • 0 answers
    44 views

    Documenting SV+OVM code in MS word preserving the format and syntax highlights

    Hi,

    As part of documenting the project work i need to copy certain code snippet of my test bench to MS word.
    I use emacs as my editor, but when i copy the code to MS word it is loosing syntax highlights and looking like a normal plain text.

    How should i preserve the format and syntax highlighting of the code in MS word.

    i would be thankful if someone tells me how to do it.

    Thanks in advance.

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    1 month 3 weeks ago - No activity yet
  • 1 answer
    5,296 views

    Top - Down and Bottom - Up Approach

    Why is the build() phase in OVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion?
    Why isn't the connect phase not executed Top - Down just like build()?
    Is there a specific reason to this?

    Thanks in Advance
    Jijo

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    Last Activity 1 month 4 weeks ago by vishalkewlani
  • 1 answer
    92 views

    Assertion checking in OVM

    I want to check that one signal at one level of rtl is always equal other signal in down the hierarchy
    of rtl after some configuration is done.

    I am having a ovm sequence which is configuring registers, after configuration is done i want check this
    assertion. Let me know in what all methods this can be done.

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    Last Activity 2 months 1 week ago by cool_cake20
  • 2 answers
    147 views

    Converting a module to/using a module in OVM?

    We have a SV module that I need to port over to OVM. What is a good resource for that? The module basically takes two interfaces and copies data from one to the other based on a config.

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    Last Activity 2 months 1 week ago by jdubrow
  • 2 answers
    4,574 views

    use of ovm_algorithmic_comparator in scoreboard implimentation

    Hi ,

    can anybody explain with small example how i can use ovm_algorithmic_comparator to impliment score board .

    Thanks
    Basavaraj hakari

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    Last Activity 2 months 2 weeks ago by poorvaag
  • 1 answer
    5,247 views

    assertion to check edge triggering

    I’m trying to write an assertion to “Verify that the TMS output changes on the falling edge of TCK.” Is this possible? It sounds simple, but I’m running into a few issues.

    The most obvious solution in my mind was to just see if it is $stable:

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    Last Activity 3 months 2 days ago by rexjohn4u
  • 1 answer
    155 views

    Implementation of transaction delay in Scoreboard

    3 packets are coming to score board, 1 and 2 packets came properly, but last packet comes with delay of 10, then how to detect this delay in scoreboard without using assertion VIP and waveform viewer. How to implement it in scoreboard?

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    Last Activity 4 months 1 week ago by manoj_k86
  • 1 solution
    153 views

    Randomization of time delay #t us. How to ?

    Hello everyone,

    Is it possible to randomize the time delay in order to create random sequences? What I mean is for example,

    forever loop
    begin
    sig_value = 1'b1;
    #10ns
    sig_value = 1_b0;
    # random_delay
    end

    Can someone shed light on how to do this? Thank you in advance.

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    Last Activity 4 months 1 week ago by Tudor Timi
  • 5 answers
    8,670 views

    importance of the clone( ) method

    Hi ALL,

    Can anybody tell me the exact application of the clone methos?
    What is the significance of the clone method?

    Regards,
    Ankit.

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    Last Activity 4 months 2 weeks ago by ranjithkumar d
  • 1 solution
    6,513 views

    Ovm & uvm rgm

    Hi,

    I heard that cadence has a RGM package available for ovm. Is there any where I can find more info about it? Will it be integrated into UVM?

    How do you compare the RAL and RGM in terms of re-usability, tool support, basic concepts, sim performance, and pros and cons?

    thanks

    Richard

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    Last Activity 4 months 2 weeks ago by hctseng
  • 1 answer
    4,017 views

    raise/drop objections issues on reset

    Hi,

    I'm implementing reset test, which generally contains loop with two threads, one generate typical flow sequences and the other wait random time, push a reset to the environment. and so on...
    my environment support reset, means scorboards, sequencers and all the other components know how to reset themselves on reset time.

    The problem is, some of my flow sequences contains raise and drop objections, and it seems that the sequencer stop_sequences() kill thus sequences but doesn't drop their objections, cause my test to stuck at the end.

    is there any recommended method to handle this issue?

    Thanks,
    Nadav

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    Last Activity 4 months 2 weeks ago by dave_59
  • 0 answers
    112 views

    How to call userdefined callback with the call of ovm_fatal

    Hi,

    I was trying to set some delay before the simulation actually stops (when we call `ovm_fatal).
    Below is the code which I was trying. But the problem with this code is the call back is function not a task, so I cannot add delay in that. How can this be done?

    import ovm_pkg::*;

    class my_object extends ovm_report_object;
    `ovm_object_utils(my_object)
    virtual function bit report_fatal_hook( string id, string message, int verbosity, string filename, int line);
    $display("My callback hook");
    return 1;
    endfunction
    endclass

    class my_test extends ovm_test;
    `ovm_component_utils(my_test)
    my_object obj;
    ovm_report_handler rh;

    function new (string name="my_test", ovm_component parent=null);
    super.new(name, parent);
    obj = my_object::type_id::create("my_object");
    endfunction : new

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    5 months 1 week ago - No activity yet
  • 1 answer
    143 views

    Compilation error : An abstract (virtual) class cannot be instantiated. and Package common_ovm_pkg could not be bound.

    Hi All,
    I have not set the OVM_HOME. i.e. echo $OVM_HOME gives OVM_HOME: Undefined variable.
    When I am running a test, I am getting the below errors:

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    Last Activity 5 months 1 week ago by dave_59
  • 0 answers
    128 views

    get_item_done results error when using also get_response

    hi,
    i am using the code below trying to avoid blocking the sequencer, using "item_done" just tight after the "get_next_item".
    my sequence using get_response to compare the actual_data to expected data.
    on the time i'm doing the item_done - i get an comparison error since the reurned item got a random data and not the actual data is should have at the end.( when (put,rsp,xact_id) is done).
    also , when the code reaches : get_response(rsp, req.get_transaction_id()) i got the following message : Dropping response for sequence %0d, sequence not found. Probable cause: sequence exited or has been killed

    how can i solve it?
    thx ze'ev

    the code :

    my code is :
    task run();
    forever begin
    seq_item_port.get_next_item(req);
    send_to_dut(req, rsp);
    seq_item_port.item_done(rsp);
    end
    endtask : run

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    5 months 2 weeks ago - No activity yet