Doubt is connect a VHDL DUT With an SV Interface!!!
This is first declaration of a signal in vhdl like below::
type t_ar7_0 is array (natural range<>) of std_logic_vector(7 downto 0);
This they have used to create a packed dimensional in vhdl for a port signal in the top module as given below::
ABC_MMM : out t_ar7_0(1 to 8);
So its like 7 to 0 of 1 to 8 signal in vhdl...
Now I had declared a counter part in interface to connect this module as logic [1:8] [7:0] abc_mmm;
Now, in a module how to connect these two signals,, I tried like this but its giving illegal port connect for VHDL type.
// DUT instance
ABC abc_dut (.ABC_MMM(interface.abc_mmm));
How can i Connect a sort of array port declaration in VHDL with SV interface!!!
Quite urgent help out plz..
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