- 3 answers4,874 views
The fatal error I am receiving while trying to simulate my compiled code is:
The interface port 'HDD_if' must be passed an actual interface.
I have included the coding i have done in posts below.
I have tried the code without using clocking blocks also. Still was encountering the same problem. I am using Questa 6.5c and my DUV is in VHDL. I am new to OVM and verification. I am doing this as part of my 1year PG project. Hope I would receive some help in here. Thanking u in advance.Last Activity 4 days 12 hours ago by devbilaye
- 3 answers5,541 views
I've just tried to use set_global_timeout() in my testbench and noticed some strange behaviour. I was hoping someone could point out the gotcha that I'm missing.
I assumed that in order to set a watchdog timeout value of 1us, I would need to add the following line to my build() function:
However, this doesn't have the desired effect. Instead the time units don't seem to be being obeyed and are out by a factor of 1000.
set_global_timeout(1s) results in a timeout after 1ms.
set_global_timeout(1ms) results in a timeout after 1us. set_global_timeout(1us) results in a timeout after 1ns.
set_global_timeout(1ns) results in a timeout after 1ps.
set_global_timeout(1000) results in a timeout after 1ns.
set_global_timeout(1000000) results in a timeout after 1us.
Thanks, Shareef.Last Activity 2 weeks 3 days ago by dave_59
- 0 answers36 views
As part of documenting the project work i need to copy certain code snippet of my test bench to MS word.
I use emacs as my editor, but when i copy the code to MS word it is loosing syntax highlights and looking like a normal plain text.
How should i preserve the format and syntax highlighting of the code in MS word.
i would be thankful if someone tells me how to do it.
Thanks in advance.1 month 1 week ago - No activity yet
- 1 answer5,253 views
Why is the build() phase in OVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion?
Why isn't the connect phase not executed Top - Down just like build()?
Is there a specific reason to this?
Thanks in Advance
JijoLast Activity 1 month 1 week ago by vishalkewlani
- 1 answer76 views
I want to check that one signal at one level of rtl is always equal other signal in down the hierarchy
of rtl after some configuration is done.
I am having a ovm sequence which is configuring registers, after configuration is done i want check this
assertion. Let me know in what all methods this can be done.Last Activity 1 month 3 weeks ago by cool_cake20
- 2 answers133 views
We have a SV module that I need to port over to OVM. What is a good resource for that? The module basically takes two interfaces and copies data from one to the other based on a config.Last Activity 1 month 3 weeks ago by jdubrow
- 2 answers4,569 views
can anybody explain with small example how i can use ovm_algorithmic_comparator to impliment score board .
Basavaraj hakariLast Activity 2 months 2 days ago by poorvaag
- 1 answer5,221 views
I’m trying to write an assertion to “Verify that the TMS output changes on the falling edge of TCK.” Is this possible? It sounds simple, but I’m running into a few issues.
The most obvious solution in my mind was to just see if it is $stable:Last Activity 2 months 2 weeks ago by rexjohn4u
- 1 answer141 views
3 packets are coming to score board, 1 and 2 packets came properly, but last packet comes with delay of 10, then how to detect this delay in scoreboard without using assertion VIP and waveform viewer. How to implement it in scoreboard?Last Activity 3 months 3 weeks ago by manoj_k86
- 1 solution135 views
Is it possible to randomize the time delay in order to create random sequences? What I mean is for example,
sig_value = 1'b1;
sig_value = 1_b0;
Can someone shed light on how to do this? Thank you in advance.Last Activity 3 months 3 weeks ago by Tudor Timi
- 1 solution6,484 views
I heard that cadence has a RGM package available for ovm. Is there any where I can find more info about it? Will it be integrated into UVM?
How do you compare the RAL and RGM in terms of re-usability, tool support, basic concepts, sim performance, and pros and cons?
RichardLast Activity 3 months 4 weeks ago by hctseng
- 1 answer4,007 views
I'm implementing reset test, which generally contains loop with two threads, one generate typical flow sequences and the other wait random time, push a reset to the environment. and so on...
my environment support reset, means scorboards, sequencers and all the other components know how to reset themselves on reset time.
The problem is, some of my flow sequences contains raise and drop objections, and it seems that the sequencer stop_sequences() kill thus sequences but doesn't drop their objections, cause my test to stuck at the end.
is there any recommended method to handle this issue?
NadavLast Activity 4 months 49 min ago by dave_59
- 0 answers101 views
I was trying to set some delay before the simulation actually stops (when we call `ovm_fatal).
Below is the code which I was trying. But the problem with this code is the call back is function not a task, so I cannot add delay in that. How can this be done?
class my_object extends ovm_report_object;
virtual function bit report_fatal_hook( string id, string message, int verbosity, string filename, int line);
$display("My callback hook");
class my_test extends ovm_test;
function new (string name="my_test", ovm_component parent=null);
obj = my_object::type_id::create("my_object");
endfunction : new4 months 2 weeks ago - No activity yet
- 1 answer126 views
Compilation error : An abstract (virtual) class cannot be instantiated. and Package common_ovm_pkg could not be bound.
I have not set the OVM_HOME. i.e. echo $OVM_HOME gives OVM_HOME: Undefined variable.
When I am running a test, I am getting the below errors:Last Activity 4 months 3 weeks ago by dave_59
- 0 answers117 views
i am using the code below trying to avoid blocking the sequencer, using "item_done" just tight after the "get_next_item".
my sequence using get_response to compare the actual_data to expected data.
on the time i'm doing the item_done - i get an comparison error since the reurned item got a random data and not the actual data is should have at the end.( when (put,rsp,xact_id) is done).
also , when the code reaches : get_response(rsp, req.get_transaction_id()) i got the following message : Dropping response for sequence %0d, sequence not found. Probable cause: sequence exited or has been killed
how can i solve it?
the code :
my code is :
endtask : run5 months 2 days ago - No activity yet
- 1 answer124 views
In the OVM source code for `ovm_field_array_object, `M_OVM_FIELD_ARRAY_OBJ_PACK macro is being called.
Under this macro (M_OVM_FIELD_ARRAY_OBJ_PACK) definition, for OVM_UNPACK case:Last Activity 5 months 3 days ago by dave_59
- 0 answers107 views
In my project i have 2 agents.I am transmitting both agents expected data from driver to Score board using analysis port.And in between driver and score board i want to put input monitor and my doubts are
How to implement input monitor in ovm environment?
Is it possible to take single monitor to both agents?
and in which block it will create and connect?
With out input monitor can i transfer expected data from driver to score board instead off input monitor to score board?5 months 6 days ago - No activity yet
- 0 answers102 views
What is the significance of
function new(string n="test" ovm_component p=null);
Does it mean object of ovm_component is null or handle to parent is null??
What super.new(n,p) will execute(i'm not sure whether it is a right word to use)?5 months 1 week ago - No activity yet