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  • 1 solution
    32 views

    Issues when download examples

    I want to download the attached examples in OVM cookbook, for example the file name is examplea.tgz, but when I start download it, its name becomes example.gz, and the file downloaed is useless. I tried many times and no one works. What's the problem?

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    Last Activity 2 days 16 hours ago by webskyforest
  • 2 answers
    4,446 views

    Coverage For SPI, I2C? Which Points to add ?

    Hi,

    I am new-bee to OVM, but fine with SV. I have been assigned work with writing Coverage for I2C and SPI interface.

    But when see the protocol I2C has just 3 output lines and so for SPI hardly 4. I am pretty confused on what to write as coverage and coverpoint.

    Can anyone spark an idea or give a sample for these protocl on which point to cover for coverage. Its an urgent task, help me.

    Br/
    Jolie Dizoza

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    Last Activity 4 days 11 hours ago by sagar@aceic.com
  • 1 solution
    75 views

    OVM_Scoreboard

    Hi,

    I have three different agent in my verification environment. All agent have analysis export to sent transaction to my scoreboard. So i have connect all analysis export to single scoreboard analysis import port.During simulation all agent call write method in different time & different sequence based on test-case.

    So, How can i manage different transaction received from different agent in scoreboard.? Can i declare multiple write method for all analysis export in scoreboard.?

    Looking for your response on the same.

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    Last Activity 3 weeks 1 day ago by Kachhadia Manoj
  • 1 answer
    74 views

    OVM

    In My Test Bench.global_stop_request() is calling automatically at 70usec .. So i am not able to completely run my sequence.

    Can anyone suggest me

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    Last Activity 3 weeks 5 days ago by therupesh
  • 1 answer
    114 views

    ovm test environment setting : hdl module vs interface

    Hi!
    I am a new user of ovm (I used to work with vhdl/verilog based verification methodology)
    I am trying to develop a verification environment for a design that communicates with an external adc( spi protocol: cs, sclk etc)

    Here is my questions:
    1-
    As I need a model to emulate the behaviour of the adc,
    should I design it as a systemverilog module ? or directly as an interface ?

    2-
    If the adc's SV model exists, can I use it as is.
    (this model contains/checks all of the adc features ( timing verification of the protocol, data in/data out serialization etc)

    Thank you.

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    Last Activity 4 weeks 1 day ago by imed_mabrouk
  • 2 answers
    95 views

    Configuration Requests Check in Sequence

    How to Write Verify Configuration Requests in PCie.
    If want to do back to back Configuration write followed by Configuration read transaction. How to perform data checking in sequence. can any one tell me.

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    Last Activity 1 month 2 weeks ago by rameshyadav472
  • 0 answers
    30 views

    Starting Address of Type0 Configuration Space in Pcie

    What is the Starting Address of Type0 configuration Space ? I am Generating Register Model for Configuration space , shall i give starting address as 32'h00 and generate register model according byte offsets ?

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    1 month 2 weeks ago - No activity yet
  • 1 answer
    93 views

    Clarification on virtual sequence and virtual sequencer in OVM or UVM

    I am trying to create a virtual sequence to control stimulus generation at SOC level using the low level sequences.
    The cook book explains two approaches
    1) using virtual sequences that gets handles to all sequencers and start the sequence on any of them
    2) use the virtual sequence and start it on a virtual sequencer which will have handles to all of the low level sequencers.

    What is the difference and how to implement 2)? There are examples on 1) in cookbook but for 2)- I dont find any

    I preferred 2) because then the virtual sequence need not be tied to know all the env sequencers.

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    Last Activity 1 month 2 weeks ago by vishnuprasanth
  • 1 answer
    76 views

    Related to Callbacks

    Hi,

    What are Callbacks in OVM.

    How they are used and which component consists of callbacks.

    Thanks
    Bharath

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    Last Activity 1 month 2 weeks ago by vishnuprasanth
  • 1 answer
    63 views

    Best practice recommendation for analysis transaction broadcast to multiple subscribers

    Hello

    I was wondering what the accepted best practice is for transmitting and receiving transactions via OVM TLM. On transmission I can understand the philosophy to 'clone on TX' since the originator owns the original handle and may decide to alter it after TX. Also - there is a chance that a downstream subscriber could corrupt the handle also.

    What about RX though? Even using 'clone on TX' - you could have multiple subscribers that will all have the same (cloned) handle presented on their respective analysis exports. Should you also 'clone on RX' - since there is no guarantee on what other subscribers may do to that handle? Is this an overly defensive mindset ... obviously the more cloning the more memory usage so performance may suffer.

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    Last Activity 1 month 2 weeks ago by vishnuprasanth
  • 1 answer
    103 views

    how to configure macros

    Hi,

    Every TB Consists of macros such ovm_info,ovm_error,...so on macro.

    I want configure this macros with some name,Can we do it,If so what should be done.

    Exactly what i want is "ovm_info" should be "new_macro_info"

    i think we can do it by `define but iam not able to write that,If someone knows how to change macros please help me.

    Thanks
    Bharath

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    Last Activity 2 months 2 days ago by dave_59
  • 1 solution
    5,897 views

    Multiple Analysis ports in the monitor

    Hi,

    Can I have multiple analysis ports in my monitor. I wanted to use this coz, my TB has two agents which can bot send/ receive a packet and I want to seperate them totally with two analysis ports

    Thanks,
    Praveen

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    Last Activity 2 years 9 months ago by praveen581
  • 3 answers
    158 views

    Running truly parallel sequences on same physical sequencer

    Hi,
    My agent has a sequencer connected to a driver of some HW interface (CIO), this protocol defines several layers of which I can run.
    1. single transaction, read/write transactions.
    2. burst of single transaction, burst is marked with start/end signals.

    so our sequences are built in layers.
    1. A sequence that run single transaction
    2. A sequence that run a list of single transactions, wrapped with grab/ungrab of the sequencer.

    my intention is to create a bunch of read bursts, in one sequence (using virtual seqr)
    and another bunch of write bursts (again, using virtual seqr) and to fork them in parallel so I'll be able to get on the bus a mix interleaved bursts of read and writes.

    What I actually get is the writes and after that the reads, no interleaved bursts.

    no wait for a response from driver in any of the sequences.

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    Last Activity 2 months 1 week ago by Uriel
  • 7 answers
    6,926 views

    two sequencers in an agent

    Can I have two sequencers in an agent, that are connected to a single driver. Is this compliant to the OVM?

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    Last Activity 2 months 3 weeks ago by Tanmoy Roy
  • 7 answers
    6,213 views

    ovm_driver/virtual interface and bi-directional bus

    I am trying to write a ovm_driver for an external processor BFM. This processor has a bi-directional tri-statable bus. How would one declare a bi-directional signal in a SystemVerilog interface?

    I tried this:

      interface cpu_if( input bit reset, input bit clk );
        logic [31:0] ad;     // Address/Data
        bit          ale;    // Address Latch Enable
    
      modport cpu_mp( inout ad, output ale, ... );
      modport per_mp( inout ad, input  ale, ... );
    
      endinterface : cpu_if
    

    When I compile this interface, I get an error:

    Quote:
    An inout port (ad) must be a net type.

    I changed ad definition to: wire [31:0] ad;

    But not in the ovm_driver, I tried driving ad and ale signals:

      up_if.ad   <= 'hz;
      up_if.ale  <= 1'b0;
    

    And I get the following error:

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    Last Activity 2 months 3 weeks ago by Kachhadia Manoj
  • 1 answer
    86 views

    ovm_test_top?

    When we run a testcase either through command line or through the run_test() method we always get the hierarchy starting with ovm_test_top.env.agent....

    From where and how we are getting ovm_test_top? i am expecting "mytest" to be there..

    Can anyone please explain?

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    Last Activity 3 months 6 days ago by cgales
  • 1 answer
    90 views

    Passing control reg values to Line side

    How does one pass DUT control register contents to Line side monitor/data item ? Host side writes value of N to DUT register. Now I need N serial bits to be sent from Line side and collect these N of them in the line monitor. I am kinda of new to ovm and i am using cadence iuc9.2 tool. Thanks.

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    Last Activity 3 months 1 week ago by sameer_kadam75
  • 1 answer
    80 views

    Questasim related

    hi i am beginner in learning OVM methodology, i may request you to guide how to add ovm 2.1.2 library kit with questa sim in windows platform.
    thanks in advance.

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    Last Activity 3 months 2 weeks ago by dave_59
  • 0 answers
    136 views

    OVM : Ovm register model W1C property

    Hi,

    I am using ovm_register-2.1. I think this package of ovm register is having some issue with W1C property of register field. As per W1C property, field should be cleared only when we write it to 1. As per implementation it is also clearing data whenever it is written to 0, too. I think it is because of following code implementation.

    calculated_value =
    ((((~new_value & W0SETMASK) | // #1
    ( new_value & ~W1CLRMASK))) // #2
    & (WMASK&local_mask)) // #3
    | (current_value & ~(WMASK&local_mask)); // #4

    So here as per case #2 W1C field will always be written to 0 up-on write. Where as I think it should not get cleared when it is written to 0.

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    3 months 2 weeks ago - No activity yet
  • 6 answers
    5,149 views

    cosimulate SystemVerilog and python

    Hi all,

    We built a high level model in python, we made use of the scipy library to quickly test some things. Now we're building a verification environment in SystemVerilog using the OVM. We would like to use the python implementation as a golden model. Therefor we need to cosimulate python and SystemVerilog, but I couldn't find any documentation whether this is possible? (We're using Questa). Any ideas?

    thanks a lot,

    Pieter

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    Last Activity 3 months 2 weeks ago by PotentialVentures