- 1 answer16 views
I want to download the attached examples in OVM cookbook, for example the file name is examplea.tgz, but when I start download it, its name becomes example.gz, and the file downloaed is useless. I tried many times and no one works. What's the problem?Last Activity 3 hours 46 min ago by Administrator
- 1 solution70 views
I have three different agent in my verification environment. All agent have analysis export to sent transaction to my scoreboard. So i have connect all analysis export to single scoreboard analysis import port.During simulation all agent call write method in different time & different sequence based on test-case.
So, How can i manage different transaction received from different agent in scoreboard.? Can i declare multiple write method for all analysis export in scoreboard.?
Looking for your response on the same.Last Activity 2 weeks 3 days ago by Kachhadia Manoj
- 1 answer107 views
I am a new user of ovm (I used to work with vhdl/verilog based verification methodology)
I am trying to develop a verification environment for a design that communicates with an external adc( spi protocol: cs, sclk etc)
Here is my questions:
As I need a model to emulate the behaviour of the adc,
should I design it as a systemverilog module ? or directly as an interface ?
If the adc's SV model exists, can I use it as is.
(this model contains/checks all of the adc features ( timing verification of the protocol, data in/data out serialization etc)
Thank you.Last Activity 3 weeks 3 days ago by imed_mabrouk
- 2 answers92 views
How to Write Verify Configuration Requests in PCie.
If want to do back to back Configuration write followed by Configuration read transaction. How to perform data checking in sequence. can any one tell me.Last Activity 1 month 1 week ago by rameshyadav472
- 0 answers28 views
What is the Starting Address of Type0 configuration Space ? I am Generating Register Model for Configuration space , shall i give starting address as 32'h00 and generate register model according byte offsets ?1 month 1 week ago - No activity yet
- 1 answer91 views
I am trying to create a virtual sequence to control stimulus generation at SOC level using the low level sequences.
The cook book explains two approaches
1) using virtual sequences that gets handles to all sequencers and start the sequence on any of them
2) use the virtual sequence and start it on a virtual sequencer which will have handles to all of the low level sequencers.
What is the difference and how to implement 2)? There are examples on 1) in cookbook but for 2)- I dont find any
I preferred 2) because then the virtual sequence need not be tied to know all the env sequencers.
- 1 answer60 views
I was wondering what the accepted best practice is for transmitting and receiving transactions via OVM TLM. On transmission I can understand the philosophy to 'clone on TX' since the originator owns the original handle and may decide to alter it after TX. Also - there is a chance that a downstream subscriber could corrupt the handle also.
What about RX though? Even using 'clone on TX' - you could have multiple subscribers that will all have the same (cloned) handle presented on their respective analysis exports. Should you also 'clone on RX' - since there is no guarantee on what other subscribers may do to that handle? Is this an overly defensive mindset ... obviously the more cloning the more memory usage so performance may suffer.
- 1 answer99 views
Every TB Consists of macros such ovm_info,ovm_error,...so on macro.
I want configure this macros with some name,Can we do it,If so what should be done.
Exactly what i want is "ovm_info" should be "new_macro_info"
i think we can do it by `define but iam not able to write that,If someone knows how to change macros please help me.
BharathLast Activity 1 month 3 weeks ago by dave_59
- 1 solution5,884 views
Can I have multiple analysis ports in my monitor. I wanted to use this coz, my TB has two agents which can bot send/ receive a packet and I want to seperate them totally with two analysis ports
PraveenLast Activity 2 years 9 months ago by praveen581
- 3 answers155 views
My agent has a sequencer connected to a driver of some HW interface (CIO), this protocol defines several layers of which I can run.
1. single transaction, read/write transactions.
2. burst of single transaction, burst is marked with start/end signals.
so our sequences are built in layers.
1. A sequence that run single transaction
2. A sequence that run a list of single transactions, wrapped with grab/ungrab of the sequencer.
my intention is to create a bunch of read bursts, in one sequence (using virtual seqr)
and another bunch of write bursts (again, using virtual seqr) and to fork them in parallel so I'll be able to get on the bus a mix interleaved bursts of read and writes.
What I actually get is the writes and after that the reads, no interleaved bursts.
no wait for a response from driver in any of the sequences.Last Activity 2 months 6 days ago by Uriel
- 7 answers6,202 views
I am trying to write a ovm_driver for an external processor BFM. This processor has a bi-directional tri-statable bus. How would one declare a bi-directional signal in a SystemVerilog interface?
I tried this:
interface cpu_if( input bit reset, input bit clk ); logic [31:0] ad; // Address/Data bit ale; // Address Latch Enable modport cpu_mp( inout ad, output ale, ... ); modport per_mp( inout ad, input ale, ... ); endinterface : cpu_if
When I compile this interface, I get an error:Quote:
An inout port (ad) must be a net type.
I changed ad definition to:
wire [31:0] ad;
But not in the ovm_driver, I tried driving ad and ale signals:
up_if.ad <= 'hz; up_if.ale <= 1'b0;
And I get the following error:Last Activity 2 months 2 weeks ago by Kachhadia Manoj
- 1 answer85 views
When we run a testcase either through command line or through the run_test() method we always get the hierarchy starting with ovm_test_top.env.agent....
From where and how we are getting ovm_test_top? i am expecting "mytest" to be there..
Can anyone please explain?Last Activity 3 months 2 days ago by cgales
- 1 answer88 views
How does one pass DUT control register contents to Line side monitor/data item ? Host side writes value of N to DUT register. Now I need N serial bits to be sent from Line side and collect these N of them in the line monitor. I am kinda of new to ovm and i am using cadence iuc9.2 tool. Thanks.Last Activity 3 months 1 week ago by sameer_kadam75
- 0 answers133 views
I am using ovm_register-2.1. I think this package of ovm register is having some issue with W1C property of register field. As per W1C property, field should be cleared only when we write it to 1. As per implementation it is also clearing data whenever it is written to 0, too. I think it is because of following code implementation.
((((~new_value & W0SETMASK) | // #1
( new_value & ~W1CLRMASK))) // #2
& (WMASK&local_mask)) // #3
| (current_value & ~(WMASK&local_mask)); // #4
So here as per case #2 W1C field will always be written to 0 up-on write. Where as I think it should not get cleared when it is written to 0.3 months 1 week ago - No activity yet
- 6 answers5,140 views
We built a high level model in python, we made use of the scipy library to quickly test some things. Now we're building a verification environment in SystemVerilog using the OVM. We would like to use the python implementation as a golden model. Therefor we need to cosimulate python and SystemVerilog, but I couldn't find any documentation whether this is possible? (We're using Questa). Any ideas?
thanks a lot,
PieterLast Activity 3 months 2 weeks ago by PotentialVentures
- 0 answers86 views
how can i pass a variable value to multiple components in multiple agents during run in ovm?
Can anyone please tell me how to do this.
Thanks in advance.3 months 2 weeks ago - No activity yet