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  • 0 answers
    10 views

    Documenting SV+OVM code in MS word preserving the format and syntax highlights

    Hi,

    As part of documenting the project work i need to copy certain code snippet of my test bench to MS word.
    I use emacs as my editor, but when i copy the code to MS word it is loosing syntax highlights and looking like a normal plain text.

    How should i preserve the format and syntax highlighting of the code in MS word.

    i would be thankful if someone tells me how to do it.

    Thanks in advance.

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    1 day 12 hours ago - No activity yet
  • 1 answer
    5,165 views

    Top - Down and Bottom - Up Approach

    Why is the build() phase in OVM executed in a Top - Down fashion and the other phases in Bottom - Up fashion?
    Why isn't the connect phase not executed Top - Down just like build()?
    Is there a specific reason to this?

    Thanks in Advance
    Jijo

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    Last Activity 4 days 6 hours ago by vishalkewlani
  • 1 answer
    33 views

    Assertion checking in OVM

    I want to check that one signal at one level of rtl is always equal other signal in down the hierarchy
    of rtl after some configuration is done.

    I am having a ovm sequence which is configuring registers, after configuration is done i want check this
    assertion. Let me know in what all methods this can be done.

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    Last Activity 2 weeks 2 days ago by cool_cake20
  • 2 answers
    90 views

    Converting a module to/using a module in OVM?

    We have a SV module that I need to port over to OVM. What is a good resource for that? The module basically takes two interfaces and copies data from one to the other based on a config.

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    Last Activity 2 weeks 3 days ago by jdubrow
  • 2 answers
    4,548 views

    use of ovm_algorithmic_comparator in scoreboard implimentation

    Hi ,

    can anybody explain with small example how i can use ovm_algorithmic_comparator to impliment score board .

    Thanks
    Basavaraj hakari

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    Last Activity 3 weeks 5 days ago by poorvaag
  • 1 answer
    5,181 views

    assertion to check edge triggering

    I’m trying to write an assertion to “Verify that the TMS output changes on the falling edge of TCK.” Is this possible? It sounds simple, but I’m running into a few issues.

    The most obvious solution in my mind was to just see if it is $stable:

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    Last Activity 1 month 1 week ago by rexjohn4u
  • 1 answer
    112 views

    Implementation of transaction delay in Scoreboard

    3 packets are coming to score board, 1 and 2 packets came properly, but last packet comes with delay of 10, then how to detect this delay in scoreboard without using assertion VIP and waveform viewer. How to implement it in scoreboard?

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    Last Activity 2 months 2 weeks ago by manoj_k86
  • 1 solution
    108 views

    Randomization of time delay #t us. How to ?

    Hello everyone,

    Is it possible to randomize the time delay in order to create random sequences? What I mean is for example,

    forever loop
    begin
    sig_value = 1'b1;
    #10ns
    sig_value = 1_b0;
    # random_delay
    end

    Can someone shed light on how to do this? Thank you in advance.

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    Last Activity 2 months 2 weeks ago by Tudor Timi
  • 5 answers
    8,335 views

    importance of the clone( ) method

    Hi ALL,

    Can anybody tell me the exact application of the clone methos?
    What is the significance of the clone method?

    Regards,
    Ankit.

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    Last Activity 2 months 3 weeks ago by ranjithkumar d
  • 1 solution
    6,427 views

    Ovm & uvm rgm

    Hi,

    I heard that cadence has a RGM package available for ovm. Is there any where I can find more info about it? Will it be integrated into UVM?

    How do you compare the RAL and RGM in terms of re-usability, tool support, basic concepts, sim performance, and pros and cons?

    thanks

    Richard

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    Last Activity 2 months 3 weeks ago by hctseng
  • 1 answer
    3,972 views

    raise/drop objections issues on reset

    Hi,

    I'm implementing reset test, which generally contains loop with two threads, one generate typical flow sequences and the other wait random time, push a reset to the environment. and so on...
    my environment support reset, means scorboards, sequencers and all the other components know how to reset themselves on reset time.

    The problem is, some of my flow sequences contains raise and drop objections, and it seems that the sequencer stop_sequences() kill thus sequences but doesn't drop their objections, cause my test to stuck at the end.

    is there any recommended method to handle this issue?

    Thanks,
    Nadav

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    Last Activity 2 months 3 weeks ago by dave_59
  • 0 answers
    79 views

    How to call userdefined callback with the call of ovm_fatal

    Hi,

    I was trying to set some delay before the simulation actually stops (when we call `ovm_fatal).
    Below is the code which I was trying. But the problem with this code is the call back is function not a task, so I cannot add delay in that. How can this be done?

    import ovm_pkg::*;

    class my_object extends ovm_report_object;
    `ovm_object_utils(my_object)
    virtual function bit report_fatal_hook( string id, string message, int verbosity, string filename, int line);
    $display("My callback hook");
    return 1;
    endfunction
    endclass

    class my_test extends ovm_test;
    `ovm_component_utils(my_test)
    my_object obj;
    ovm_report_handler rh;

    function new (string name="my_test", ovm_component parent=null);
    super.new(name, parent);
    obj = my_object::type_id::create("my_object");
    endfunction : new

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    3 months 1 week ago - No activity yet
  • 1 answer
    89 views

    Compilation error : An abstract (virtual) class cannot be instantiated. and Package common_ovm_pkg could not be bound.

    Hi All,
    I have not set the OVM_HOME. i.e. echo $OVM_HOME gives OVM_HOME: Undefined variable.
    When I am running a test, I am getting the below errors:

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    Last Activity 3 months 2 weeks ago by dave_59
  • 0 answers
    94 views

    get_item_done results error when using also get_response

    hi,
    i am using the code below trying to avoid blocking the sequencer, using "item_done" just tight after the "get_next_item".
    my sequence using get_response to compare the actual_data to expected data.
    on the time i'm doing the item_done - i get an comparison error since the reurned item got a random data and not the actual data is should have at the end.( when (put,rsp,xact_id) is done).
    also , when the code reaches : get_response(rsp, req.get_transaction_id()) i got the following message : Dropping response for sequence %0d, sequence not found. Probable cause: sequence exited or has been killed

    how can i solve it?
    thx ze'ev

    the code :

    my code is :
    task run();
    forever begin
    seq_item_port.get_next_item(req);
    send_to_dut(req, rsp);
    seq_item_port.item_done(rsp);
    end
    endtask : run

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    3 months 3 weeks ago - No activity yet
  • 1 answer
    107 views

    OVM 2.1.2 bug: Issue with macro `ovm_field_array_object

    In the OVM source code for `ovm_field_array_object, `M_OVM_FIELD_ARRAY_OBJ_PACK macro is being called.
    Under this macro (M_OVM_FIELD_ARRAY_OBJ_PACK) definition, for OVM_UNPACK case:

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    Last Activity 3 months 3 weeks ago by dave_59
  • 0 answers
    85 views

    Creation and usage of input monitor in ovm?

    In my project i have 2 agents.I am transmitting both agents expected data from driver to Score board using analysis port.And in between driver and score board i want to put input monitor and my doubts are
    How to implement input monitor in ovm environment?
    Is it possible to take single monitor to both agents?
    and in which block it will create and connect?
    With out input monitor can i transfer expected data from driver to score board instead off input monitor to score board?

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    4 months 9 hours ago - No activity yet
  • 0 answers
    83 views

    Factory and Configuration

    What is the difference between factory and configuration table?

    How factory and configurations are implemented?

    Where factory and configuration settings are stored?

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    4 months 1 day ago - No activity yet
  • 0 answers
    82 views

    new()

    Hi,
    What is the significance of

    function new(string n="test" ovm_component p=null);
    super.new(n,p);
    endfunction

    Does it mean object of ovm_component is null or handle to parent is null??

    What super.new(n,p) will execute(i'm not sure whether it is a right word to use)?

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    4 months 1 day ago - No activity yet
  • 0 answers
    91 views

    type_id::create

    Hi,

    I came across the following statements while learning OVM regarding "create" method:

    class my_component extends base_component;
    my_driver driver;
    ...
    function build();
    driver = my_driver::type_id::create("driver",this);
    ...
    endfunction
    endclass

    And the explanation was :: "The
    type_id::create()method is a type-specific static method that returns an instance of the
    desired type (in this case, my_driver) from the factory. The arguments to create()are the
    same as the standard constructor arguments, a string name and a parent component.The
    use of the factory allows the developer to derive a new class extended from my_driver and
    cause the factory to return the extended type in place of my_driver. Thus, the parent
    component can use the new type without modifying the parent class
    ."

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    4 months 1 day ago - No activity yet
  • 4 answers
    6,171 views

    what is the difference between ovm_transaction and ovm_sequence_item????

    Hi Sir,

    I am working on AXI 1.0 now and truing to develop AXI OVC. I used `ovm_sequence_item for generating sequences for APB protocol.But for AXI one of my college told me use `ovm_transaction instead of `ovm_sequence_item. what shall i use `ovm_sequence_item or `ovm_transation to generate the sequences.

    what is the difference between them.
    how does the below code works,how are they different from one another????
    where the difference comes????

    Please guide me

    class master_transfer extends `ovm_transaction;
    rand [31:0] waddr;
    rand [31:0] wdata;
    rand [3:0] wsize;
    rand [31:0] wlength;

    //factory registration

    //

    endclass

    class master_transfer extends `ovm_sequence_item;
    rand [31:0] waddr;
    rand [31:0] wdata;
    rand [3:0] wsize;
    rand [31:0] wlength;

    //factory registration

    //

    endclass

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    Last Activity 6 months 1 week ago by dave_59