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  • Tutorial for Gate Level Simulation

Tutorial for Gate Level Simulation

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gate level simulation 1
Reuben
Reuben
Full Access
186 posts
May 19, 2016 at 6:30 pm

Is there a tutorial here on how to do gate level simulations? I've tried to do some research but the topics I've seen here are more in UVM and System Verilog but none for gate level simulations.

I'm not asking how to do it using any tools. What I need are the proper way on creating a testbench for a gate level simulation.
In my experience, my testbench is running good on RTL simulations but on gate level simulations some problems suddenly appear like my assertions are failing because of glitches, sampling of data by the monitor is wrong, etc.

So, do you have any tutorial for do's and dont's on creating a test bench for gate level simulations?

Thanks.

Regards,
Reuben

Replies

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yogeshraut712
yogeshraut712
Forum Access
7 posts
August 23, 2017 at 2:20 am

In reply to Reuben:
Hello Reuben,

Could you be able to share with me information regarding how to perform (steps) Gate Level Simulations, and commands that are to be used for GLS on Mentor Graphics or Other company EDA tools.

I have been looking for answers all over the internet but not able to find reliable source. I have developed verification environment using SystemVerilog and I have actually converted my RTL design into Gate level netlist but I want to know commands and steps involved in performing simple GLS.

regards,
Yogesh

Reuben
Reuben
Full Access
186 posts
August 24, 2017 at 4:46 am

In reply to yogeshraut712:

Hi Yogesh. That was also my problem before. There are no good resources in the Internet to learn Gate Level Simulation. So I just learned from doing it in my job. I cannot give you the commands since it is not allowed here in the Verification Academy to discuss tool-related things.

GLS can be better learned by doing it rather than by reading. Maybe one of the hindrance why there are no tutorials in internet is because they don't know where to get the cell library.

I guess it is good if Verification Academy can add a tutorial here.=)

dave_59
dave_59
Forum Moderator
7899 posts
August 24, 2017 at 10:44 am

In reply to Reuben:

One reason for the lack of resources on GLS is the fact that there are so few people left doing it. FPGAs can no longer be represented accurately for GLS, and formal tools handle gate-level topologies with much better accuracy.

- Dave Rich

Reuben
Reuben
Full Access
186 posts
August 28, 2017 at 7:38 pm

In reply to dave_59:

I see. I would like to learn how to use those Formal tools too. I hope there are tutorials online. I don't think I can be able to ask my employer to train me for it. They already have a particular team that does that.

bmamta
bmamta
Full Access
1 post
January 15, 2018 at 11:04 am

In reply to dave_59:

Quote:
In reply to Reuben:

One reason for the lack of resources on GLS is the fact that there are so few people left doing it. FPGAs can no longer be represented accurately for GLS, and formal tools handle gate-level topologies with much better accuracy.

Hi Dave,

Is there a tutorial explaining formal Vs dynamic simulation for GLS. What are benefits of using one over another for design types.

kansagaratushar
kansagaratushar
Full Access
18 posts
August 16, 2019 at 2:19 am

In reply to dave_59:

I don't know how to work with GLS in Questa 10.0b ?? so I have to add any library for that? how to add-in Questa? I got netlist file with no include (.edn) file but giving the error like :

Module 'LUT2' is not defined

if I include (.edn) then give error as :

edif.edn(1): near "(": syntax error, unexpected '(', expecting class

What i have to do? replay as soon as possible

dave_59
dave_59
Forum Moderator
7899 posts
August 16, 2019 at 8:45 am

In reply to kansagaratushar:

EDIF is another format that needs to be converted to Verilog before running a simulation.

- Dave Rich

kansagaratushar
kansagaratushar
Full Access
18 posts
August 17, 2019 at 12:47 am

In reply to dave_59:

// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//`include "dct_edif.edn"

(* STRUCTURAL_NETLIST = "yes" *)
module dct_dut
(CLK,
RST,
xin,
z_out);
input CLK;
input RST;
input [7:0]xin;
output [10:0]z_out;

its in verilog file and other .edn file we got at time of netlist conversion so i replaced rtl file with netlist file. i add xilinks library files added in project.

what I have to do now ?? if you can provide GLS verification small example. that's will be very helpful.

dave_59
dave_59
Forum Moderator
7899 posts
August 17, 2019 at 7:56 am

In reply to kansagaratushar:

This forum is not for tool specific help. Check your tool's documentation for simulation tutorials.

- Dave Rich

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