Is there a tutorial here on how to do gate level simulations? I've tried to do some research but the topics I've seen here are more in UVM and System Verilog but none for gate level simulations.
I'm not asking how to do it using any tools. What I need are the proper way on creating a testbench for a gate level simulation.
In my experience, my testbench is running good on RTL simulations but on gate level simulations some problems suddenly appear like my assertions are failing because of glitches, sampling of data by the monitor is wrong, etc.
So, do you have any tutorial for do's and dont's on creating a test bench for gate level simulations?
Thanks.
Regards,
Reuben
