Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Visualizer Debug - October 27th
      • Fault Campaign Management - October 29th
      • Events Calendar

    • On Demand Seminars

      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
      • Bottoms-Up Safety Analysis
      • Memory Modeling - DDR VIP
      • All On-Demand Seminars

    • Recording Archive

      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • What’s New in Functional Verification
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • UVM Framework
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • Questa Simulation Coverage Acceleration Apps with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - July 2020
      • Verification Horizons - March 2020
      • Verification Horizons - December 2019
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
Ask a Question
Downloads
  • Home /
  • Forums /
  • Downloads /
  • Tutorial for Gate Level Simulation

Tutorial for Gate Level Simulation

Downloads 94
gate level simulation 1
Reuben
Reuben
Full Access
185 posts
May 19, 2016 at 6:30 pm

Is there a tutorial here on how to do gate level simulations? I've tried to do some research but the topics I've seen here are more in UVM and System Verilog but none for gate level simulations.

I'm not asking how to do it using any tools. What I need are the proper way on creating a testbench for a gate level simulation.
In my experience, my testbench is running good on RTL simulations but on gate level simulations some problems suddenly appear like my assertions are failing because of glitches, sampling of data by the monitor is wrong, etc.

So, do you have any tutorial for do's and dont's on creating a test bench for gate level simulations?

Thanks.

Regards,
Reuben

Replies

Log In to Reply
yogeshraut712
yogeshraut712
Forum Access
7 posts
August 23, 2017 at 2:20 am

In reply to Reuben:
Hello Reuben,

Could you be able to share with me information regarding how to perform (steps) Gate Level Simulations, and commands that are to be used for GLS on Mentor Graphics or Other company EDA tools.

I have been looking for answers all over the internet but not able to find reliable source. I have developed verification environment using SystemVerilog and I have actually converted my RTL design into Gate level netlist but I want to know commands and steps involved in performing simple GLS.

regards,
Yogesh

Reuben
Reuben
Full Access
185 posts
August 24, 2017 at 4:46 am

In reply to yogeshraut712:

Hi Yogesh. That was also my problem before. There are no good resources in the Internet to learn Gate Level Simulation. So I just learned from doing it in my job. I cannot give you the commands since it is not allowed here in the Verification Academy to discuss tool-related things.

GLS can be better learned by doing it rather than by reading. Maybe one of the hindrance why there are no tutorials in internet is because they don't know where to get the cell library.

I guess it is good if Verification Academy can add a tutorial here.=)

dave_59
dave_59
Forum Moderator
8200 posts
August 24, 2017 at 10:44 am

In reply to Reuben:

One reason for the lack of resources on GLS is the fact that there are so few people left doing it. FPGAs can no longer be represented accurately for GLS, and formal tools handle gate-level topologies with much better accuracy.

- Dave Rich

Reuben
Reuben
Full Access
185 posts
August 28, 2017 at 7:38 pm

In reply to dave_59:

I see. I would like to learn how to use those Formal tools too. I hope there are tutorials online. I don't think I can be able to ask my employer to train me for it. They already have a particular team that does that.

bmamta
bmamta
Full Access
1 post
January 15, 2018 at 11:04 am

In reply to dave_59:

Quote:
In reply to Reuben:

One reason for the lack of resources on GLS is the fact that there are so few people left doing it. FPGAs can no longer be represented accurately for GLS, and formal tools handle gate-level topologies with much better accuracy.

Hi Dave,

Is there a tutorial explaining formal Vs dynamic simulation for GLS. What are benefits of using one over another for design types.

kansagaratushar
kansagaratushar
Full Access
18 posts
August 16, 2019 at 2:19 am

In reply to dave_59:

I don't know how to work with GLS in Questa 10.0b ?? so I have to add any library for that? how to add-in Questa? I got netlist file with no include (.edn) file but giving the error like :

Module 'LUT2' is not defined

if I include (.edn) then give error as :

edif.edn(1): near "(": syntax error, unexpected '(', expecting class

What i have to do? replay as soon as possible

dave_59
dave_59
Forum Moderator
8200 posts
August 16, 2019 at 8:45 am

In reply to kansagaratushar:

EDIF is another format that needs to be converted to Verilog before running a simulation.

- Dave Rich

kansagaratushar
kansagaratushar
Full Access
18 posts
August 17, 2019 at 12:47 am

In reply to dave_59:

// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//`include "dct_edif.edn"

(* STRUCTURAL_NETLIST = "yes" *)
module dct_dut
(CLK,
RST,
xin,
z_out);
input CLK;
input RST;
input [7:0]xin;
output [10:0]z_out;

its in verilog file and other .edn file we got at time of netlist conversion so i replaced rtl file with netlist file. i add xilinks library files added in project.

what I have to do now ?? if you can provide GLS verification small example. that's will be very helpful.

dave_59
dave_59
Forum Moderator
8200 posts
August 17, 2019 at 7:56 am

In reply to kansagaratushar:

This forum is not for tool specific help. Check your tool's documentation for simulation tutorials.

- Dave Rich

© Mentor, a Siemens Business, All rights reserved www.mentor.com

Footer Menu

  • Sitemap
  • Terms & Conditions
  • Verification Horizons Blog
  • LinkedIn Group
SiteLock