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  • I2C Verification environment using the UVM

I2C Verification environment using the UVM

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uvm 4 i2c testbench 1
Carsten Thiele
Carsten Thiele
Full Access
6 posts
January 18, 2012 at 9:34 am
Contributor: Carsten Thiele
Date: January 18, 2012  
Description: The contribution is UVM based I2C testbench for the I2C master device that can be downloaded from opencores.org. It is guaranteed to work out of the box with Questasim 10.1.

The TB makes use of CRT and SVA.

A README file with an explanation of the TB structure and instructions on how to run tests and regressions can be found under iic/docs/HowTo.txt.

The implementation largely follows the recommendations of Mentor's UVM Cookbook.

  
Download: iicTb.tar_.gz  

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ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2657 posts
January 18, 2012 at 11:49 am

In this model you use in /iic/iic_tb/test/iicPcTest/iicPcTest.svh
phase.raise_objection(this,"iicPcTest");

What is the difference between uvm_test_done. and phase.?
* uvm_test_done.raise_objection(this);
* phase.raise_objection(this,"iicPcTest");

Also, which is better use?
Ben

Carsten Thiele
Carsten Thiele
Full Access
6 posts
January 20, 2012 at 5:25 am

In reply to ben@SystemVerilog.us:

Hi Ben,

to be honest, this is just boiler plate code. I wasn't aware that there are alternatives and hence I can't tell you anything about their respective merrits. Thanks, however, for drawing my attention to this.

Cheers,

Carsten

mperyer
mperyer
Forum Moderator
284 posts
January 28, 2012 at 11:51 am

uvm_test_done.raise_objection() is a hangover from the OVM where it was used to end the run phase.

phase.raise_objection() raises objections for a particular phase (of which there are several) and is therefore more suitable for the UVM since it allows fine grained control for controlling when to complete a particular phase.

mangello
mangello
Full Access
16 posts
November 20, 2012 at 9:25 am

In reply to mperyer:

Is this code accessible anymore?

System Administrator
System Administrator
Administrator
74 posts
November 20, 2012 at 11:29 am

In reply to mangello:

Hi Mangello,

The link to file download has been corrected. You can download it now.

mangello
mangello
Full Access
16 posts
November 25, 2012 at 8:46 am

In reply to System Administrator:

After I unzip this file what do I use to view it?

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2657 posts
November 25, 2012 at 1:13 pm

In reply to mangello:

For your convenience, I uploaded the file that I had.
http://systemverilog.us/iicTb.tar_.gz // original download
http://systemverilog.us/iic.zip // zipped from expanded directory
Ben Cohen

sxu1
sxu1
Full Access
4 posts
January 22, 2013 at 11:54 am

In reply to ben@SystemVerilog.us:

Hello Ben,
I am new to UVM. I have some serial interface design. Should I use the approach as I2C Verification environment using the UVM, or should I use parallel-to-serial approach? Is there other methods which you can recommend?
Thanks,
sxu1

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