Trasition between signals

Coverage
1

Hello,

Is it possible to have a coverpoint or a cover property that covers the transition of one signal to another signal, respecting UVM rules? (I use a uvm_subscriber to extend a new class for my coverage)

For example, I have three bit signals “A”, “B” and “C”. I want to cover that afer the assertion and deassertion of signal “A” I will eventually have the assertion of “B” and not the assertion of “C”. And similarly, after the assertion of “B” I will eventually have the assertion of “C” and not of “A”.

I though about something like:


covergroup mySignals;
    //cover set and reset
    coverpoint A {
        bins set_A = {1};
        bins reset_A = {0};
    }
    coverpoint B {
        bins set_B = {1};
        bins reset_B = {0};
    }
    coverpoint C {
        bins set_C = {1};
        bins reset_C = {0};
    }
    //cover transition, option1:
    coverpoint ({A,B}) {
        bins trans_A2B = (2'b10 => 2'b01):
        ignore_bins trans_B2A = (2'b01 => 2'b10); // that helps to now if there is any count, but it does not check that this transition must not occur
    }
endgroup

But the problem that I see with this option is that it will only counts when the transition is in the next clock cycle, not in the future. Another option that I have seen is:


//option2:
cover property (a&&!b |=> ##[1:5] b);

But this option cannot go inside of the class.

Can you help me?
Please if you did not understand my problem ask what you need!

Thanks!!

2

In reply to germanbravolopez:

I consider the implementation details would depend on your requirements, of course you could develop an entire environment using OOP and UVM with the coverage collector, but for this kind of cases I’m more inclined to use cover properties, you could encapsulate them in a coverage collector module that can be connected using SV bindings and can be reused for future projects or in multiple places in the design.

I have to ask why having something outside a class is an issue for you?

At the end of the day the verification process consists of multiple approaches and techniques that aim for the same goal.

One thing is not clear from your description is the end goal do you want to check this signals’ behaviour or do you need to cover it, there’re some differences in terms implementing the checker part and then developing the coverage to measure

Here you can find some examples of using bindings
https://www.sunburst-design.com/papers/CummingsSNUG2016SV_SVA_Best_Practices.pdf

HTH,

-R