Systemverilog cross coverage with intersect

Coverage
, ,
1

I want to cross as following

[A[1],B[1],c[1]]
[A[2],B[2],c[1]]
[A[3],B[3],c[1]]
.
.
.
[A[31],B[31],c[1]]

Note that A and B values to be crossed must be same i.e. when A = 5, B value also has to be 5.
Here is my code:
//////////////////////////////////////

bit [31:0] A,B;
bit [1:0] C;

cp_A : coverpoint a {
bins eq0 = {1'b0};
bins eq1_31 = [1:31];
}

cp_B : coverpoint b {
bins eq0 = {1'b0};
bins eq1_31 = [1:31];
}

cp_C : coverpoint c {
bins eq0 = {1'b0};
bins eq0 = {1'b1};

cross_abc : cross a,b,c {
ignore_bins ignore00 = binsof(cp_A.eq0);
ignore_bins ignore01 = binsof(cp_B.eq0);
ignore_bins ignore02 = binsof(cp_C.eq0);
bins isect_cross = binsof(cp_B.eq1_31)intersect{[1:31}};
}

I am not getting any error but I am not sure if my intended cross is achieved. Is my code correct?

2

In reply to salmee:

Tons of typos in your example. I think the following is what you want. Remember that with a cross, the only things you can do with bins is ignore or combine sets of bins tuples.

  covergroup cg;
      
      cp_A : coverpoint a {
	 bins eq0 = {1'b0};
	 bins eq1_31[] = {[1:31]};
      }
      
      cp_B : coverpoint b {
	 bins eq0 = {1'b0};
	 bins eq1_31[] = {[1:31]};
      }
      
      cp_C : coverpoint c {
	 bins eq0 = {1'b0};
	 bins eq1 = {1'b1};
      }
      
      x_abc : cross cp_A,cp_B,cp_C {
	 ignore_bins ignore00 = binsof(cp_A.eq0);
	 ignore_bins ignore01 = binsof(cp_B.eq0);
	 ignore_bins ignore02 = binsof(cp_C.eq0);
	 ignore_bins not_equal = x_abc with (cp_A != cp_B);
      }
   endgroup