Systemverilog coding for assertion to check valid and ready for a specific number of clks to check burst

Hi,

I would like to check an architecture feature for a general ready/valid interface.
The input “valid” becomes 1 when valid data is output with it.
The output “ready” becomes 1 after reset. “ready” becomes zero when the input buffer becomes full.
When ready==1 && valid==1 after a macro defined value of 14,
then ready is output to 0.

I only want to check this once for a specific test because this burst check may not apply to other tests.

Any testbench qualifier I need to only allow assertion to trigger for a particular testcase ?

`define BURST_LENGTH 14

`ifdef TC2
assert_check_burst_length: assert property(@(posedge clk) disable iff(rst) 
	    $rose(ready&&valid)][->1] |=>  $stable(ready&&valid)[*BURST_LENGTH] else $error();
`endif


In reply to davidct:

To fire once put the assertion in an initial block.
Ben systemverilog.us