SystemVerilog can perform statistical analysis of computer systems. Unlike other verification techniques like UVM that verify that the design meets the requirements, statistical analysis of the system can bring out more details about the system and can challenge the sanity of the requirements. For this arbiter design, the analysis demonstrated the weakness of changing the level of arbitration with a simple countdown rather than a countdown following a completed transaction, i.e., a request followed by a grant. The analysis also demonstrated the need to define the system load environment because that determines the system performance in terms of latencies, such as delays between a request and a grant. The greatest difficulty in doing statistical analysis is the definition of those statistical inputs, and it’s the old GIGO issue.
Readers of this paper may appreciate the design approach angle for the arbiter, the usage of assertion coverage along with SystemVerilog covergroup and coverpoint.
http://systemverilog.us/vf/arbiterv426a.sv
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
- Free books: Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb - Papers:
- Understanding the SVA Engine,
Verification Horizons - Reflections on Users’ Experiences with SVA
Reflections on Users’ Experiences with SVA - SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue - SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
Udemy courses by Srinivasan Venkataramanan (http://cvcblr.com/home.html)
https://www.udemy.com/course/sva-basic/
https://www.udemy.com/course/sv-pre-uvm/