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  • Sampling covergroup when a FSM state ends

Sampling covergroup when a FSM state ends

Coverage 561
#coverage 55 #covergroup 6
Ariel Elliassi
Ariel Elliassi
Full Access
15 posts
August 31, 2022 at 4:22 am

Hello,
I have a covergroup that I want to sample when a specific state of the FSM ends.
For example, when state_1 ends (and the next state is different) then the group should be sampled.

One way I thought of doing it, is to have 2 variable of cur_state and next_state in my coverage file, and in the main_phase task compare them and if they are different then sample.

Is there a more elegant way? I have inspiration from transition sampling in bins (STATE_1 => STATE_2) or iff of some kind.

Thank you

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dave_59
dave_59
Forum Moderator
11263 posts
August 31, 2022 at 10:36 am

In reply to Ariel Elliassi:

The elegant way is using a cover directive instead of a covergroup

cover property (@(posedge clk) cur_state==STATE_1 |-> cur_state!=STATE_1[->1]);

But if this code needs be be in a class, you will have to resort to less elegant ways.

You could use a range if that works out for your states

bins end_state_1 = (STATE_1 => [STATE_2:STATE_N]);

— Dave Rich, Verification Architect, Siemens EDA

Ariel Elliassi
Ariel Elliassi
Full Access
15 posts
September 01, 2022 at 1:28 am

In reply to dave_59:

Thank you very much.
About the second solution, is it possible/correct to write it as:

bins end_state_1 = (STATE_1 => (~STATE_1));

So basically, transition from STATE_1 to anything else?

Also, I need to sample a value when STATE_1 ends, so if I'll do a cross between a value and a transition, will it give the value at the time the state ends?

dave_59
dave_59
Forum Moderator
11263 posts
September 01, 2022 at 1:19 pm

In reply to Ariel Elliassi:

That will not work because Kit just inverts the bits of the encoding for STATE_1, which may or may not be another valid state encoding.

I think we are getting into sn XY problem. You should call sample() on the variable you want covered the the code in your task detects that it has exited STATE_1

— Dave Rich, Verification Architect, Siemens EDA

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