$rose, $fell not accepted in iff condition?

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1

I am trying to cover the active and inactive run-lengths of a signal.

I made a counter that increments when the signal is stable and resets on a transition.

always @(posedge clk) begin
  if ($stable(sig))
    counter <= counter + 1;
  else
    counter <= 1;
end

I thought I could then cover the “active” run-lengths by defining a coverpoint on the counter with the additional condition to only count it after the signal “fell” and similarly cover the “inactive” run-lengths with a coverpoint that only counts after the signal rises:

covergroup count_active_inactive @(posedge clk);
  inactive: coverpoint counter iff ($rose(sig)) {bins cycles[] = {1,2,3,[4:$]};}
  active:   coverpoint counter iff ($fell(sig)) {bins cycles[] = {1,2,3,[4:$]};}
endgroup

However, the compiler tells me that this type of use of $rose/$fell is illegal.

“Illegal use of sampled value function outside concurrent assertions and procedural blocks”

Is there a way to circumvent this or should I really not be doing it this way in the first place?

2

In reply to RickN:

$rose/$fall will not work inside covergroup. Declare 2 variable eg : int sig_rise, sig_fall. Then in always block assign
if($rose(sig)) begin
sig_rise = 5;
counter <= counter + 1;
end
else if($fall(sig)) begin
sig_fall = 10;
counter <= 1;
end

Now capture the “active”/inactive run_length by checking the signal variable values.
coverpoint counter iff(sig_rise == 5) {
bins cycles = {1,2,3,[4:$]};
}
Try in this way.

3

In reply to srvm:

I chose to simulate the functionality of $rose and $fell by maintaining a 1-cycle delayed copy of the signal for which I’m counting run-lenghts and looking at the difference between the 2.

4

You could make this much simpler if you just called the sample method inside your always block. This would also improve performance.

covergroup count_active_inactive;
  inactive: coverpoint counter iff (sig) {bins cycles[] = {1,2,3,[4:$]};}
  active:   coverpoint counter iff (!sig) {bins cycles[] = {1,2,3,[4:$]};}
endgroup

count_active_inactive cai = new();
always @(posedge clk) begin
  if ($stable(sig))
    counter <= counter + 1;
  else begin
      cai.sample(); 
      counter <= 1;
    end
end
5

In reply to dave_59:

What is the reason for not supporting $rose/$fell inside covergroup?(which had clocking event declared: @(posedge clk))

6

In reply to Naven8:

Possibly for no other reason that SystemVerilog was designed by committee. It is very difficult for people who add features to the language to think of all possible interactions with every feature of the language.

7

In reply to dave_59:

Thanks Dave.