Hi all,
I need to cross two cover_point, and ignore part of transition bins.
rec_sel_module_cfg_cp: coverpoint rec_sel_module_cfg{
bins rec_sel_module_cfg_cp.MODULE = {[1:10]};
bins AMTI_UP_TRANS[] = (6,7,8,9,10 => 6,7,8,9,10);
bins RANGE_TO_UP_TRANS[] = (0,1,2,3,4,5 => 6,7,8,9,10);
bins UP_TO_RANGE_TRANS[] = (6,7,8,9,10 => 0,1,2,3,4,5);
}
amti_clk_cp: coverpoint amti_clk {
bins CLK_250 = {250};
bins CLK_300 = {300};
}
clk_with_amti_c: cross amti_clk_cp,rec_sel_module_cfg_cp {
ignore_bins AMTI_CLK = binsof (rec_sel_module_cfg_cp.MODULE) intersect {6,7,9};
ignore_bins AMTI_CLK_6_7_9 = binsof (rec_sel_module_cfg_cp.AMTI_UP_TRANS) intersect {(6,7,9 => 6,7,9)};
ignore_bins AMTI_CLK_X_6 = binsof (rec_sel_module_cfg_cp.RANGE_TO_UP_TRANS) intersect {(0,1,2,3,4,5 => 6,7,9)};
ignore_bins AMTI_CLK_6_X = binsof (rec_sel_module_cfg_cp.UP_TO_RANGE_TRANS) intersect {(6,7,9 => 0,1,2,3,4,5)};
}
I want that bins will be created only when rec_sel_module_cfg is 6,7,9 or transition between 6,7,9 to any number, but there is an error with the syntax:
Error-[SE] Syntax error
Following verilog source has syntax error :
58: token is ‘,’, column 92
ignore_bins AMTI_CLK_6_7_9 = binsof
(rec_sel_module_cfg_cp.AMTI_UP_TRANS) intersect {(6,7,9 => 6,7,9)};
Is anyone has a solution?
Thanks