Hi,
I am new to SystemVerilog coverage. i am trying out few things.
covergroup Timer_cov (int max) with function sample( virtual interface Timer_fcov_if vif);
tmr_load_count_cp : coverpoint vif.timer_count{
bins tmr_count = {max} ; }
endgroup :Timer_cov
From test i am trying to sample/pass max value to covergroup but it is taking default value of int 0.
class test extends uvm_test();
..
..
Timer_cov tmr_cg;
int count=200;
function new();
tmr_cg = new (count);
endfunction
task main_phase()
tmr_cg.sample(timer_if);
endtask
endclass
any help is appreciated.
In reply to prema9998:
Not enough code to explain what might be going wrong. What is the value of timer_count when you call sample?
In reply to dave_59:
Timer_count value is 32 bit random value. It can be any value between 0 to 2^32. I want to sample timer count with respect to max.i want to know how to pass max value from test.
In reply to prema9998:
You wrote a covergroup passing an argument (max) to the constructor. The value of the argument is 200, so you will hit on the single bin tar_count when timer_count == 200. For this covergroup, you can either have 0% coverage, or 100$ when timer_count == 200.
You need to explain in words what you need to get 100% coverage. I do not know what “sample timer count with respect to max” means. In what respect?