How to ignore 'rest of bins' in cross coverage

Coverage
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1

I’m trying to write coverpoints for specific sequences of instructions in a pipeline:

pipe_stage_0: coverpoint({stage_0_is_inst_A, stage_0_is_inst_B})
{
   bins IS_A = {2'b10};
   bins IS_B = {2'b01};
   bins IS_NEITHER = {2'b00};
}

pipe_stage_1: coverpoint({stage_1_is_inst_A, stage_1_is_inst_B})
{
   bins IS_A = {2'b10};
   bins IS_B = {2'b01};
   bins IS_NEITHER = {2'b00};
}

pipe_stage_2: coverpoint({stage_2_is_inst_A, stage_2_is_inst_B})
{
   bins IS_A = {2'b10};
   bins IS_B = {2'b01};
   bins IS_NEITHER = {2'b00};
}

pipe_inst_cross: cross pipe_stage_0, pipe_stage_1, pipe_stage_2
{
   bins A_B_NEITHER = binsof(pipe_stage_0.IS_A) && binsof(pipe_stage_1.IS_B) && binsof(pipe_stage_2.IS_NEITHER);
   bins A_A_NEITHER = binsof(pipe_stage_0.IS_A) && binsof(pipe_stage_1.IS_A) && binsof(pipe_stage_2.IS_NEITHER);
   bins NEITHER_A_B = binsof(pipe_stage_0.IS_NEITHER) && binsof(pipe_stage_1.IS_A) && binsof(pipe_stage_2.IS_B);
   ... // a few other explicit sequences I want to include
   // somehow ignore remainder bins?
}

The coverage report certainly shows these explicit bins, but unfortunately it also autogenerates every other combination of the cross. (The latter greatly outnumbers the former.)

How can I ignore those remainder bins? I have tried

ignore_bins ignore_invalid = default;

but it seems this is not allowed in a cross statement.

2

In reply to atashinchi:

The current LRM only allows combining autogenerated cross bins, or ignoring them. You have a couple of choices:

Use another coverpoint instead of a cross

pipe_inst_cross: coverpoint  { stage_0_is_inst_A, stage_0_is_inst_B, 
                               stage_1_is_inst_A, stage_1_is_inst_B,
                               stage_2_is_inst_A, stage_2_is_inst_B }
{
   bins A_B_NEITHER = { {2'b10, 2'b01, 2'b00} };
   bins A_A_NEITHER = { {2'b10, 2'b10, 2'b00} };
   bins NEITHER_A_B = { {2'b00, 2'b10, 2'b01} };
}

Use more coverpoints instead of more bins

pipe_stage_0_IS_A: coverpoint({stage_0_is_inst_A, stage_0_is_inst_B})
{
   bins IS_A = {2'b10};
}
pipe_stage_0_IS_B: coverpoint({stage_0_is_inst_A, stage_0_is_inst_B})
{
   bins IS_B = {2'b01};
}
pipe_stage_0_IS_NEITHER: coverpoint({stage_0_is_inst_A, stage_0_is_inst_B})
{
   bins IS_NEITHER = {2'b00};
}
 
pipe_stage_1_IS_A: coverpoint({stage_1_is_inst_A, stage_1_is_inst_B})
{
   bins IS_A = {2'b10};
}
...
pipe_stage_2_IS_NEITHER: coverpoint({stage_2_is_inst_A, stage_2_is_inst_B})
{
   bins IS_NEITHER = {2'b00};
}

Then cross the specific coverpoints you need.

A_B_NEITHER: cross pipe_stage_0_IS_A,pipe_stage_1_IS_B, pipe_stage_2_IS_NEITHER;
A_A_NEITHER: cross pipe_stage_0_IS_A,pipe_stage_1_IS_A, pipe_stage_2_IS_NEITHER;
NEITHER_A_B: cross pipe_stage_0_IS_NEITHER,pipe_stage_1_IS_A, pipe_stage_2_IS_B;

Note there is an enhancement coming in the next revision of the IEEE 1800 SystemVerilog LRM with a new option
cross_retain_auto_bins that prevents autogeneration of cross bins. Ask your tool vendor about support.

3

In reply to atashinchi:

If you insist on default-bin like behavior within cross , here is Dave’ solution using ignore_bins