In reply to atashinchi:
The current LRM only allows combining autogenerated cross bins, or ignoring them. You have a couple of choices:
Use another coverpoint instead of a cross
pipe_inst_cross: coverpoint { stage_0_is_inst_A, stage_0_is_inst_B,
stage_1_is_inst_A, stage_1_is_inst_B,
stage_2_is_inst_A, stage_2_is_inst_B }
{
bins A_B_NEITHER = { {2'b10, 2'b01, 2'b00} };
bins A_A_NEITHER = { {2'b10, 2'b10, 2'b00} };
bins NEITHER_A_B = { {2'b00, 2'b10, 2'b01} };
}
Use more coverpoints instead of more bins
pipe_stage_0_IS_A: coverpoint({stage_0_is_inst_A, stage_0_is_inst_B})
{
bins IS_A = {2'b10};
}
pipe_stage_0_IS_B: coverpoint({stage_0_is_inst_A, stage_0_is_inst_B})
{
bins IS_B = {2'b01};
}
pipe_stage_0_IS_NEITHER: coverpoint({stage_0_is_inst_A, stage_0_is_inst_B})
{
bins IS_NEITHER = {2'b00};
}
pipe_stage_1_IS_A: coverpoint({stage_1_is_inst_A, stage_1_is_inst_B})
{
bins IS_A = {2'b10};
}
...
pipe_stage_2_IS_NEITHER: coverpoint({stage_2_is_inst_A, stage_2_is_inst_B})
{
bins IS_NEITHER = {2'b00};
}
Then cross the specific coverpoints you need.
A_B_NEITHER: cross pipe_stage_0_IS_A,pipe_stage_1_IS_B, pipe_stage_2_IS_NEITHER;
A_A_NEITHER: cross pipe_stage_0_IS_A,pipe_stage_1_IS_A, pipe_stage_2_IS_NEITHER;
NEITHER_A_B: cross pipe_stage_0_IS_NEITHER,pipe_stage_1_IS_A, pipe_stage_2_IS_B;
Note there is an enhancement coming in the next revision of the IEEE 1800 SystemVerilog LRM with a new option cross_retain_auto_bins that prevents autogeneration of cross bins. Ask your tool vendor about support.
