does any one has idea about generating the coverage bins from make file dynamically
In reply to abhiverif1715:
This question is very vague. “Make” is used to build scripts that run scripts tools. Your scripts can create SystemVerilog source code that have whatever bins you want based on the options you provide to it. Or you can write your SystemVerilog code to look for command line options to guide it in generating bins. Or you can just write bins for everything, and dynamically set the weights of certain bins to 0 to exclude them.
For any of these options, we would need know more about how you want dynamically modifiy your bins to make the best choices. This might be a bit complicated to do over a forum, so I suggest finding someone local in your team, or contacting your tool vendor for support.
In reply to dave_59:
Hi dave,
thanks for response let me elaborate my query,i have to take random frequency from command line lets say 100mhz and for that div value would be 2,4,5,10…100 (reminder should be 0) for div value…so i need to have cover bins as well as div_value to be same.
as my input frequcny can be anything so i need to have some kind of dynamic coverage generation approach so based on input freq i will have coverage for the div value.
In reply to abhiverif1715:
This is still not enough information. When you say you’re taking the frequency from the command line how is that getting passed to your test, and are you trying to merge coverage from different frequencies?
In reply to dave_59:
hi dave,
i am thinking to pass from $test$args is that right approach ?
yes i want to merge all the bins/per frequency.
what would be the best approach ?