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Coverage
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  • How do I collect coverage for register from multiple address locations

How do I collect coverage for register from multiple address locations

Coverage 543
#SystemVerilog ... 38
superUVM
superUVM
Full Access
43 posts
January 23, 2020 at 8:12 am 

class reg_functional_coverage extends uvm_subscriber #(axi_seq_item);
`uvm_component_utils(reg_functional_coverage) 
 
axi_reg_block regmodel;
 
covergroup reg_rw_cov;
 	option.per_instance = 1;
	MODE: coverpoint regmodel.my_Register[1:0];  
 
	RW: coverpoint regmode.my_Register[7];  
 
	RW_CROSS: cross MODE, RW;
endgroup: reg_rw_cov
 
covergroup reg_rw_cov;
 
endclass

my_Register is 8 bit. Register model contains 128 instances of my_Registers in following order
Four my_Registers are arranged in 32 bit row and there are 32 rows as shown below,

bit 31 ....................................bit0
row 0 my_Register_3 my_Register_2 my_Register_1 my_Register_0
row 1 ................................................
.
.
row 31 my_Register_127 my_Register_126 my_Register_125 my_Register_124

Access to any of these 32*4=128 my_Register should collect coverage.
I can not split my_Register in to 128 covergorups and collect coverage since Multiple covergroups can not be combined.

What is the best approach? Do you have any example?

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dave_59
dave_59
Forum Moderator
10908 posts
January 23, 2020 at 9:37 am

In reply to superUVM:

Your question is not clear. What scenario are you trying to collect coverage for?

— Dave Rich, Verification Architect, Siemens EDA

superUVM
superUVM
Full Access
43 posts
January 23, 2020 at 9:55 am

In reply to dave_59:
Any of my_register_* can be written by host. They are arranged in memory as shown above.

1)collect combined coverage of registers in bin MODE when bit [1:0] of any of 128 registers is set.
2)collect combined coverage of registers in bin RW when bit [7] of any of 128 registers is set.
3) Collect combined cross coverage of MODE and RW. i.e. Cross coverage should use bit[1:0] and bit[7] of same register. Multiple registers will be written and need to combine cross coverage of all those registers.

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