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  • How can I quantify the coverage in scenario verification?

How can I quantify the coverage in scenario verification?

Coverage 561
#coverage 55
Lily_y
Lily_y
Forum Access
1 post
June 09, 2023 at 12:29 am

I use some test patterns in System level verification.
The main purpose is to verify functionality of BUS and DDR.
But, I'm not a BUS designer but DV engineer doing prototyping SoCs.
I mainly check if the transaction is working well between CPU, BUS and DDR.

Q1. After I change the fixed test pattern to random test patten, What metrices can explain the increase in coverage?

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dave_59
dave_59
Forum Moderator
11263 posts
June 14, 2023 at 2:04 pm

In reply to Lily_y:

This seems like a very open-ended interview question. The idea behind constrained random verification is generating many test patterns quicker than you could ever write fixed patterns. More patterns, better coverage.

— Dave Rich, Verification Architect, Siemens EDA

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