Having problem with state transition coverage

Coverage
1

Hi,

I tried to cover repetition of transition coverage in my code, but it is giving a compilation error.
I made a demo example which is as per below.

Here, it is showing a_2 bin is not proper with Questasim.

module top();

  int a;

  covergroup t;
    a_d : coverpoint a
    {
      bins a[] = {[0:5]};
    }
    a_c : coverpoint a
    {
      bins a_1 = (0=>1=>2[*1:3]=>3);
      bins a_2 = (0=>(1=>2[*1:3])[*1:3]=>3);
    }
  endgroup

  initial begin
    t t= new();
    a= 0;
    t.sample();
    a= 1;
    t.sample();
    a= 2;
    t.sample();
    a= 1;
    t.sample();
    a= 2;
    t.sample();
    a= 3;
    t.sample();
  end
 
endmodule

Any body can help, how to write repetition of transition coverage?
My requirement is , there can be more than 1 (less than 4) transition of (1 => 2) in between 0 and 3.

Thanks,
Munjal

2

*In reply to mmistry@apm.com:*My requirement is , there can be more than 1 (less than 4) transition of (1 => 2) in between 0 and 3.

Consider using an assertion
cover property (a==0 |=> (a==1 ##1 a==2)[*1:4] ##1 a==3);

Ben Ben@systemverilog.us

3

In reply to ben@SystemVerilog.us:

Hi Ben,

Thank you for your help.
Can’t I write it as coverpoint bins?

Thanks,
Munjal

4

In reply to mmistry@apm.com:
You are looking for a specific set of sequences starting from a particular condition. This is an assertion.
You could write code that detects those conditions, and then do coverpoint bins on that code.
That code basically represents an assertion; you might as well use SVA. . What is yyou objection in using the cover property?
Ben Ben@systemverilog.us

5

In reply to ben@SystemVerilog.us:

Actually, I want to cover IDLE[1:N0]=>{NON_SEQ=>SEQ[1:MAX]}[1:N1]=>IDLE[1:N2] kind of transition in the covergroup for AHB.

Thanks,
Munjal

6

In reply to mmistry@apm.com:

In reply to ben@SystemVerilog.us:
Actually, I want to cover IDLE[1:N0]=>{NON_SEQ=>SEQ[1:MAX]}[1:N1]=>IDLE[1:N2] kind of transition in the covergroup for AHB.
Thanks,
Munjal

You. Could use something like the following example that demonstrate how to use variables for Dynamic range delays.
property p;

  int lv = max_delay;

  req |-> (lv > 0, lv = lv - 1)[*0:$] ##1 ack;

endproperty

A: assert property(@(posedge clk)p);
Ben

7

In reply to ben@SystemVerilog.us:

Ok. Let me try this one in top file.

Thanks,
Munjal