Generate block use inside coiverage

Coverage
1

HI,
Can we use generate block inside covergroup block ?

2

In reply to kjadav:

No. A generate block can exist at the top-level of a module, interface, or SystemVerilog checker.

You need to provide more details of what you want to accomplish if you want alternative suggestions.

3

In reply to dave_59:

Are there any other way to implement cover points array? Like use of `define macros.

4

In reply to kjadav:

Again, you need to provide more details of what you are trying to accomplish if you want alternative suggestions. What is the design requirement you are trying to cover?