Disabling illegal_bins using iffs

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1

I have some bins that I want to be illegal depending on a parameter

I have written this:

bins          mode_a = {3'b100};
illegal_bins  no_a   = {3'b100} iff (DISABLE);

Those bins work as expected. If DISABLE is true, no_a overrules mode_a and make mode_a an illegal bin. If DISABLE is false, no_a doesn’t overrule mode_a so mode_a is a valid bin.

I am trying to do the same with transitional bins:

bins          mode_a_b = (3'b100 => 3'b110);
illegal_bins  no_a_b   = (3'b100 => 3'b110) iff (DISABLE);

This does not do the same thing. Regardless of whether DISABLE is true or not, no_a_b overrules mode_a_b and makes it illegal.

Any suggestions?

2

In reply to Cmdr_Vimes:
The iff clause is not be used to specify bin creation. It only affects which bins are hit during each sample by evaluating a guard expression each time the sample occurs.

bins          mode_a = {3'b100};
illegal_bins  no_a   = {3'b100} with (DISABLE);

The with clause gets evaluated when the covergroup gets constructed.

Unfortunately, transition bins have very limited functionality in SystemVerilog and you might be better off covering a sequence instead of using a covergroup.

3

In reply to dave_59:

In my case DISABLE is a parameter.

bins          mode_a = {3'b100};
illegal_bins  no_a   = {3'b100} with (DISABLE);

does not compile and I get an error.

In the method I’m using (iff), both coverpoints get triggered but the illegal_bin only get triggered if the iff is true, so the value goes into the illegal_bin and the normal bin then becomes an illegal_bin. Is there a specific reason that it doesn’t do the same for transition bins or is it just the limited functionality?

4

In reply to Cmdr_Vimes:

I get a warning about the mode_a or no_a bin being removed, depending on the value of DISABLE, no compiler errors. It’s possible you are using a version of a tool that does not support it yet. This was an 1800-2012 feature.

There are many problems with the specification of transition bins in the LRM. Here is one of them. So I would stick with something simple, otherwise use a sequence or build your own state machine.